比特大陆台湾新竹研发中心资深后端设计工程师需求，薪资丰厚，
时间：12-12
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简历发送至：ic_trader@163.com,谢谢大家关注！
资深芯片后端设计工程师
职位描述
We're searching for senior physical design engineer who will work toghether with the talented team to execute most challenging chip design tasks. The mission of the team is to define the architecture and implement the customed ASIC chips to for high performance computing.
Key Responsibilities:
- Execute the whole Physical Design flow include Floorplan/Placement/CTS/Routing/Physical Verification
- Work with front end design Engineers to achieve timing closure for both partition level and full chip level
- IO ring design
- Cross talk Analysis
- IR Drop and Power Integrity Analysis
- Execute ECO's.
- Develop and enhance entire physical design flow at both chip and block level.
技能要求
- BS/MS in Electrical or Computer Engineering with 5+ yrs experience in physical design
- Experience with advanced process, experience with hierachical design flow.
- Hands-on experience in full-chip/sub-chip Static Timing Analysis. CPU related timing convergence background would be a plus.
- Hands on experience in logic synthesis and equivalence checking/FV required.
- Expertise in physical design and optimization e.g. placement, routing, cell sizing, buffering, logic restructuring, etc. to improve timing and power required. Background in implementing them through ECOs required.
- Understanding of DFT logic and hands-on experience in design closure taking into account DFT logic required. DFT timing closure for various modes e.g. scan shift and capture, transition faults, BIST, etc. would be a plus.
- Expertise in analyzing and converging crosstalk delay, noise glitch, and electrical/manufacturing rules in deep-sub micron processes
- Understand process variation effect modeling and experience in design convergence taking into account variations required.
- Experience in critical path planning and crafting. Experience in circuits, SPICE simulations, and/or transistor level STA would be a plus.
- Expertise and in-depth knowledge of industry standard EDA tools required.
- Proficiency in scripting languages, such as, Perl, Tcl, Make, etc. Experience in methodology and/or flow automation would be a plus.
简历发送至：ic_trader@163.com,谢谢大家关注！
资深芯片后端设计工程师
职位描述
We're searching for senior physical design engineer who will work toghether with the talented team to execute most challenging chip design tasks. The mission of the team is to define the architecture and implement the customed ASIC chips to for high performance computing.
Key Responsibilities:
- Execute the whole Physical Design flow include Floorplan/Placement/CTS/Routing/Physical Verification
- Work with front end design Engineers to achieve timing closure for both partition level and full chip level
- IO ring design
- Cross talk Analysis
- IR Drop and Power Integrity Analysis
- Execute ECO's.
- Develop and enhance entire physical design flow at both chip and block level.
技能要求
- BS/MS in Electrical or Computer Engineering with 5+ yrs experience in physical design
- Experience with advanced process, experience with hierachical design flow.
- Hands-on experience in full-chip/sub-chip Static Timing Analysis. CPU related timing convergence background would be a plus.
- Hands on experience in logic synthesis and equivalence checking/FV required.
- Expertise in physical design and optimization e.g. placement, routing, cell sizing, buffering, logic restructuring, etc. to improve timing and power required. Background in implementing them through ECOs required.
- Understanding of DFT logic and hands-on experience in design closure taking into account DFT logic required. DFT timing closure for various modes e.g. scan shift and capture, transition faults, BIST, etc. would be a plus.
- Expertise in analyzing and converging crosstalk delay, noise glitch, and electrical/manufacturing rules in deep-sub micron processes
- Understand process variation effect modeling and experience in design convergence taking into account variations required.
- Experience in critical path planning and crafting. Experience in circuits, SPICE simulations, and/or transistor level STA would be a plus.
- Expertise and in-depth knowledge of industry standard EDA tools required.
- Proficiency in scripting languages, such as, Perl, Tcl, Make, etc. Experience in methodology and/or flow automation would be a plus.
简历发送至：ic_trader@163.com,谢谢大家关注！
请注意置顶的版规，同一天不要发两个以上招聘主题贴。
怎么在新竹 北京上海 还不够吗
北京的行情…今年比较妖，随便一个做后端的，都能轻松拿高薪，供求极度不平衡。
上海还好。
大牛啊
比特大陆生意做得很大啊！ 分店都开到新竹了。
北京今年出来太多的新公司了
有多丰厚啊大哥
真的假的，有多高？
听说了。。房价惹的祸？
正解
做ic就那么一些人，突然冒出来几个公司抢人
跟房价无关
供求关系
牛人永远不愁下家
比前几年行情好多了
前几年北京找个ic工作都不容易
现在行情这么好？回光返照么？
所以就是学后端也别学模拟射频了
台湾新竹在这论坛贴能招到吗？
数字后端还是可以的
请看置底，每2天限发一个招聘贴，谢谢！
请教有哪些新公司？
你不奇怪才怪呢，嘿嘿
华捷艾米，地平线，人加，有兴趣发简历哈
看从业资历，水平，薪资不是问题。
待遇有多高
看水平的，发简历哈。。。