恩智浦（NXP）天津ASIC Design/Verification Engineer
时间：12-12
整理：3721RD
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工作地点在天津，本职位仅面向2015－2017年毕业的硕士研究生
有意者请将简历发送至 victorkai.liu@nxp.com，我们将及时和您联系。
ASIC Design/Verification Engineer
Job Description:
o Discuss with system and market on the project requirement and definition
o Designs and develops digital circuits for micro-controller and application processor.
o Verification in module level and chip level; define and execute verification plan with full functional coverage.
o Involved in the Digital IP design and verification, joins the SoC development for ARM Based MCU.
o RTL coding, integration and verification.
o Work with backend team on timing closure.
o Doing simulation in gate Level, transistor Level (full-chip spice).
o Create function test patterns for test engineering.
Job Requirement:
o Master Degree or University Degree of equivalent from Electronic, Electrical or Computer Science.
o Good knowledge in Verilog/VHDL, C. (System Verilog, C++, Perl/Tcl is a plus)
o Good communication and Inter-person skill.
o Good language skill in English, Pass CET-6.
o Understand VLSI design flow. Having sense of timing analysis is a plus.
o Having experience with simulation EDA tool is a plus.
o Having experience with Unix/Linux system is a plus.
o Having concepts on generic computer architecture is a plus.
o Having knowledge on image process/video decoding and encoding is a plus
o Understanding ARM cortex A/M architecture is a plus
o Basic knowledge of Analog and Mix-signal design and verification is a plus.
有意者请将简历发送至 victorkai.liu@nxp.com，我们将及时和您联系。
ASIC Design/Verification Engineer
Job Description:
o Discuss with system and market on the project requirement and definition
o Designs and develops digital circuits for micro-controller and application processor.
o Verification in module level and chip level; define and execute verification plan with full functional coverage.
o Involved in the Digital IP design and verification, joins the SoC development for ARM Based MCU.
o RTL coding, integration and verification.
o Work with backend team on timing closure.
o Doing simulation in gate Level, transistor Level (full-chip spice).
o Create function test patterns for test engineering.
Job Requirement:
o Master Degree or University Degree of equivalent from Electronic, Electrical or Computer Science.
o Good knowledge in Verilog/VHDL, C. (System Verilog, C++, Perl/Tcl is a plus)
o Good communication and Inter-person skill.
o Good language skill in English, Pass CET-6.
o Understand VLSI design flow. Having sense of timing analysis is a plus.
o Having experience with simulation EDA tool is a plus.
o Having experience with Unix/Linux system is a plus.
o Having concepts on generic computer architecture is a plus.
o Having knowledge on image process/video decoding and encoding is a plus
o Understanding ARM cortex A/M architecture is a plus
o Basic knowledge of Analog and Mix-signal design and verification is a plus.
up!
招聘进行中~