ASIC_Design,Project Leader
时间：12-12
整理：3721RD
点击：
280k+/year
Senior ASIC Design Engineer:
Design top-of-the-line graphics processors, including specification, architecture, micro-architecture, implementation (using Verilog), and verification
Expected skills:
3+ years hands-on experience
Programming skills in Verilog HDL
Must be familiar with all stages of the ASIC design flow (including specification, architecture, and design implementation)
Highly motivated and skillful at solving difficult technical problems
Knowledge of computer graphics and low-power design techniques a plus
Experience of GPU or compression design a plus
280k+/year
Project Leader:
Design top-of-the-line graphics processors, including specification, architecture, micro-architecture, implementation (using Verilog), and verification
Expected skills:
5+ years hands-on experience
Experience of leading a project from spec define to final release
Programming skills in Verilog HDL
Must be familiar with all stages of the ASIC design flow (including specification, architecture, and design implementation)
Highly motivated and skillful at solving difficult technical problems
Knowledge of computer graphics and low-power design techniques a plus
Experience of GPU or compression design a plus
location:Shanghai or Chengdu
If you are interested in this position, please send your resume (as attachment)
to: huiming.zhang@verisilicon.com
Senior ASIC Design Engineer:
Design top-of-the-line graphics processors, including specification, architecture, micro-architecture, implementation (using Verilog), and verification
Expected skills:
3+ years hands-on experience
Programming skills in Verilog HDL
Must be familiar with all stages of the ASIC design flow (including specification, architecture, and design implementation)
Highly motivated and skillful at solving difficult technical problems
Knowledge of computer graphics and low-power design techniques a plus
Experience of GPU or compression design a plus
280k+/year
Project Leader:
Design top-of-the-line graphics processors, including specification, architecture, micro-architecture, implementation (using Verilog), and verification
Expected skills:
5+ years hands-on experience
Experience of leading a project from spec define to final release
Programming skills in Verilog HDL
Must be familiar with all stages of the ASIC design flow (including specification, architecture, and design implementation)
Highly motivated and skillful at solving difficult technical problems
Knowledge of computer graphics and low-power design techniques a plus
Experience of GPU or compression design a plus
location:Shanghai or Chengdu
If you are interested in this position, please send your resume (as attachment)
to: huiming.zhang@verisilicon.com
今年好点的应届生都不止280k/y了。。。
硅农是远远不如码农了
洪架构v5!
没办法啊 design service和互联网差距大啊
说的就是硅工应届生的价啊
update
真的假的，28w 是应届生的价格？
想啥呢， 你仔细看一下里面有 5year +
不错，明码实价，比遮遮掩掩的强
我说上面那个兄弟说的