AMD 上海 图形处理器 Verification Engineer
时间：12-12
整理：3721RD
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AMD招前端验证工程师，三年工作经验或应届生。
简历请发送 jefwa AT $MY_COMPANY DOT com
Eng2 ASIC Design Verification Engineer (Graphics IP) /NCG(应届生)
Job Location: Shanghai
We are currently looking for engineer who will be responsible for design verification of cutting edge graphics IP blocks. Our team is essential and key to GPU in the success of AMD as a growing company. Qualified candidate will participate in the most challenging and interesting projects the industry has to offer.
Job description:
o Understand the architecture of the computer, graphics IP and functional block being designed
o Write C++ tests and build C/C++ model for simulation
o Write sequences in the UVM based test environments
o Build test bench and monitors for DUT
o Compose test plan and validation vectors to ensure functional completeness
o Debug function/performance bugs of graphics IP
o Power-aware verification
Preferred Experience:
o Major in EE, CS or related, Master Degree with 1-2 years or Bachelor with 3+ years working experiences or NCG (应届生)
o Rich knowledge on computer architecture
o Experience with design for verification (assertion based design strategies, Coverage-Driven Verification (CDV) , test plan, gate-level simulation, low power, formal verification, etc.)
o Should be familiar with any one of HW verification languages such as C/C++ and System Verilog
o Should be familiar with knowledge of industry standard tools for verification
o Strong problem solving skills, excellent communication skills (both written and oral)
o Familiar with Linux Environment (including shell scripting and linux gnu tools)
o Aggressive attitude to face challenges and passion to learn/work
o Understanding of the graphics algorithm is a big plus.
o Good knowledge on verification methodologies like UVM is a desired plus
简历请发送 jefwa AT $MY_COMPANY DOT com
Eng2 ASIC Design Verification Engineer (Graphics IP) /NCG(应届生)
Job Location: Shanghai
We are currently looking for engineer who will be responsible for design verification of cutting edge graphics IP blocks. Our team is essential and key to GPU in the success of AMD as a growing company. Qualified candidate will participate in the most challenging and interesting projects the industry has to offer.
Job description:
o Understand the architecture of the computer, graphics IP and functional block being designed
o Write C++ tests and build C/C++ model for simulation
o Write sequences in the UVM based test environments
o Build test bench and monitors for DUT
o Compose test plan and validation vectors to ensure functional completeness
o Debug function/performance bugs of graphics IP
o Power-aware verification
Preferred Experience:
o Major in EE, CS or related, Master Degree with 1-2 years or Bachelor with 3+ years working experiences or NCG (应届生)
o Rich knowledge on computer architecture
o Experience with design for verification (assertion based design strategies, Coverage-Driven Verification (CDV) , test plan, gate-level simulation, low power, formal verification, etc.)
o Should be familiar with any one of HW verification languages such as C/C++ and System Verilog
o Should be familiar with knowledge of industry standard tools for verification
o Strong problem solving skills, excellent communication skills (both written and oral)
o Familiar with Linux Environment (including shell scripting and linux gnu tools)
o Aggressive attitude to face challenges and passion to learn/work
o Understanding of the graphics algorithm is a big plus.
o Good knowledge on verification methodologies like UVM is a desired plus
硕士一年多也可以么？