IC design&test@ 复旦 上海
时间：12-12
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Prof. Patrick Yin Chiang’s research group at Fudan Univ. is looking for new MS / PhD students and Research-Associates to explore research on E3: Energy-Efficiency at the Extremes:
[1] High-Speed Optical Communications
[2] Next-Generation Optical IOT Sensing
Where: State ASIC & Key Laboratory, Fudan University, Shanghai, China
Who: Dr. Patrick Yin Chiang, 1000-Talents Professor of China
We are looking for sharp, hard-working, and open-minded students immediately or in 2017 who are interested in working together on cutting-edge research together in his group.
If interested, please Send an English-CV/resume to: patrick.chiang.osu@gmail.com
See Prof. Chiang’s website at http://homepage.fudan.edu.cn/english/patrickchiang
Contact: sophia.yang@photonic-tech.com (https://cn.linkedin.com/in/sophia-yang-61558b2a)
Job positions in PhotonIC http://www.photonic-tech.com/
Digital-ASIC Design Engineer
Positions: Junior, Senior
Salary: Competitive salary with generous stock options
Commensurate with experience/skill
Job description:
- This position is for a digital/ASIC design engineer to build next-generation analog/mixed-signal SoC chipsets.
- Handle many aspects of ASIC design flow including: architecture, RTL coding, Verification, Synthesis, DFT, STA and P&R.
- Participate in chip debug, validation, and marketing specifications.
Qualifications:
- BSEE with minimum 3-year experience or MSEE with minimum 1-year experience of digital experience.
- Excellent knowledge of ASIC design, such as arithmetic structure (addition, multiplication), timing analysis, DFT, meta-stability, etc.
- Fundamental understanding of digital signal processing, such as FIR/IIR filter structure, error correction, and decimation.
- Desired usage experience of several industry-standard EDA tools, such as VCS/NC, Design Compiler, PrimeTime, Formality/ Conformal and Tetramax/DFT compiler.
- Experience in bus design (I2C, AHB or AIX), datapath design (Filter, correlation or Cordic) and logic control (PCS or MAS) is a plus.
- Experience in metrics-driven verification methodology (System-Verilog/UVM based) is a plus.
- Experience in several vertical aspects of ASIC design (front-end and back-end) will be a great plus.
Analog / Mixed-Signal Design Engineer
Positions: Junior, Senior
Salary: Competitive salary with generous stock options
Commensurate with experience/skill
Job Description:
- You will perform analog and mixed signal design, characterization and evaluation of analog circuits such as:
high-speed amplifiers, wireline transmitters, PLL, or other baseband circuits like LDO, temp sensor, ADC, Filters, etc.
- You will optimize the design of high-frequency (multi-gigahertz) and high-precision analog circuits.
- Use EDA tools (Cadence, Mentor) to run simulation and function verification.
- Guide layout engineer to optimize layout.
- Chip debug and testing individually.
- Design and optimize chip layout.
Qualifications:
- MSEE in analog IC design with 2 years’ experience.
- Experience in Cadence EDA tools.
- Team player with good communication skills.
- Experience with SERDES transmitter/receiver, TIA, CDR, LNA etc. is highly preferred.
- Desired: Knowledge of advanced circuits such as PLLs, ADCs, DACs, LNAs, drivers, NF, S-parameters, BW extension.
- Desired: Experience in RF circuit design, testing, and post-silicon bring-up and evaluation.
Test / System Validation Engineer
Positions: Junior/Senior
Job Description:
- This job will evaluate and test several of our state-of-the-art high-speed SOC products. These include high-frequency multi-gigahertz analog/mixed-signal chips, with significant testing issues such as: channel cross talk, input-referred noise, phase noise, output bandwidth, power-supply noise, impedance matching.
Qualifications:
- Bachelor's degree with minimum 2 years’ experience as FAE, IC designer, or test engineer.
- Experience and understanding of impedance matching, noise processes, phase noise, multi-GHz performance.
- Occasionally (20%) be willing to travel to test lab and customer locations, testing our chips in their labs.
- Can read system datasheets, understand, and debug interactions between different blocks.
- Desired: previous experience with basic IC design, PCB prototyping, IC testing.
- Desired: High-level system programming, such as C/C++, python/Perl, LabView, Matlab.
- Desired: Lab experience using oscilloscopes, signal/pattern generators, BERT, spectrum analyzer, AWG, BERT.
- Preferred: Experience with high-speed optical testing, including BERT, eye mask, jitter, optical coupling, etc.
- Preferred: Experience with interfacing with ATE and wafer-level testing/sorting.
ATE: Automated Test Engineer
Positions: Junior, Senior
Job description:
- Develop ATE test programs for debug, characterization, qualification and production of SoC devices.
Qualifications:
- 3 years relevant working experience and in depth knowledge of semiconductor testing process.
- Solid understanding of high speed digital and analog circuits, design for test and manufacturing concepts.
- Expertise in Semiconductor Test Methodology.
- Experience working with Digital, Mixed Signal, and SOC Devices with hands on ATE experience.
- Strong Programming skills for writing and debugging test programs and HW related issues
- Ability to program with Scripting languages (i.e. Perl) and high level languages (i.e. C/C or Visual Basic.).
- Able to work with test equipment (i.e. VNA, DCA, Oscilloscope, etc.).
- Experience in high-speed PCB design.
Responsibilities:
- Develop and document test plan for new product.
- Work with DFT and design teams to evaluate new product testability.
- Design and debug test SW & HW for Production, Characterization & Reliability.
- Work with DFT and design teams to debug new silicon.
- Bring quality and cost effective test solution for mass production.
- Coordinate test related activities with both internal and external group.
[1] High-Speed Optical Communications
[2] Next-Generation Optical IOT Sensing
Where: State ASIC & Key Laboratory, Fudan University, Shanghai, China
Who: Dr. Patrick Yin Chiang, 1000-Talents Professor of China
We are looking for sharp, hard-working, and open-minded students immediately or in 2017 who are interested in working together on cutting-edge research together in his group.
If interested, please Send an English-CV/resume to: patrick.chiang.osu@gmail.com
See Prof. Chiang’s website at http://homepage.fudan.edu.cn/english/patrickchiang
Contact: sophia.yang@photonic-tech.com (https://cn.linkedin.com/in/sophia-yang-61558b2a)
Job positions in PhotonIC http://www.photonic-tech.com/
Digital-ASIC Design Engineer
Positions: Junior, Senior
Salary: Competitive salary with generous stock options
Commensurate with experience/skill
Job description:
- This position is for a digital/ASIC design engineer to build next-generation analog/mixed-signal SoC chipsets.
- Handle many aspects of ASIC design flow including: architecture, RTL coding, Verification, Synthesis, DFT, STA and P&R.
- Participate in chip debug, validation, and marketing specifications.
Qualifications:
- BSEE with minimum 3-year experience or MSEE with minimum 1-year experience of digital experience.
- Excellent knowledge of ASIC design, such as arithmetic structure (addition, multiplication), timing analysis, DFT, meta-stability, etc.
- Fundamental understanding of digital signal processing, such as FIR/IIR filter structure, error correction, and decimation.
- Desired usage experience of several industry-standard EDA tools, such as VCS/NC, Design Compiler, PrimeTime, Formality/ Conformal and Tetramax/DFT compiler.
- Experience in bus design (I2C, AHB or AIX), datapath design (Filter, correlation or Cordic) and logic control (PCS or MAS) is a plus.
- Experience in metrics-driven verification methodology (System-Verilog/UVM based) is a plus.
- Experience in several vertical aspects of ASIC design (front-end and back-end) will be a great plus.
Analog / Mixed-Signal Design Engineer
Positions: Junior, Senior
Salary: Competitive salary with generous stock options
Commensurate with experience/skill
Job Description:
- You will perform analog and mixed signal design, characterization and evaluation of analog circuits such as:
high-speed amplifiers, wireline transmitters, PLL, or other baseband circuits like LDO, temp sensor, ADC, Filters, etc.
- You will optimize the design of high-frequency (multi-gigahertz) and high-precision analog circuits.
- Use EDA tools (Cadence, Mentor) to run simulation and function verification.
- Guide layout engineer to optimize layout.
- Chip debug and testing individually.
- Design and optimize chip layout.
Qualifications:
- MSEE in analog IC design with 2 years’ experience.
- Experience in Cadence EDA tools.
- Team player with good communication skills.
- Experience with SERDES transmitter/receiver, TIA, CDR, LNA etc. is highly preferred.
- Desired: Knowledge of advanced circuits such as PLLs, ADCs, DACs, LNAs, drivers, NF, S-parameters, BW extension.
- Desired: Experience in RF circuit design, testing, and post-silicon bring-up and evaluation.
Test / System Validation Engineer
Positions: Junior/Senior
Job Description:
- This job will evaluate and test several of our state-of-the-art high-speed SOC products. These include high-frequency multi-gigahertz analog/mixed-signal chips, with significant testing issues such as: channel cross talk, input-referred noise, phase noise, output bandwidth, power-supply noise, impedance matching.
Qualifications:
- Bachelor's degree with minimum 2 years’ experience as FAE, IC designer, or test engineer.
- Experience and understanding of impedance matching, noise processes, phase noise, multi-GHz performance.
- Occasionally (20%) be willing to travel to test lab and customer locations, testing our chips in their labs.
- Can read system datasheets, understand, and debug interactions between different blocks.
- Desired: previous experience with basic IC design, PCB prototyping, IC testing.
- Desired: High-level system programming, such as C/C++, python/Perl, LabView, Matlab.
- Desired: Lab experience using oscilloscopes, signal/pattern generators, BERT, spectrum analyzer, AWG, BERT.
- Preferred: Experience with high-speed optical testing, including BERT, eye mask, jitter, optical coupling, etc.
- Preferred: Experience with interfacing with ATE and wafer-level testing/sorting.
ATE: Automated Test Engineer
Positions: Junior, Senior
Job description:
- Develop ATE test programs for debug, characterization, qualification and production of SoC devices.
Qualifications:
- 3 years relevant working experience and in depth knowledge of semiconductor testing process.
- Solid understanding of high speed digital and analog circuits, design for test and manufacturing concepts.
- Expertise in Semiconductor Test Methodology.
- Experience working with Digital, Mixed Signal, and SOC Devices with hands on ATE experience.
- Strong Programming skills for writing and debugging test programs and HW related issues
- Ability to program with Scripting languages (i.e. Perl) and high level languages (i.e. C/C or Visual Basic.).
- Able to work with test equipment (i.e. VNA, DCA, Oscilloscope, etc.).
- Experience in high-speed PCB design.
Responsibilities:
- Develop and document test plan for new product.
- Work with DFT and design teams to evaluate new product testability.
- Design and debug test SW & HW for Production, Characterization & Reliability.
- Work with DFT and design teams to debug new silicon.
- Bring quality and cost effective test solution for mass production.
- Coordinate test related activities with both internal and external group.