Hiring : Senior IC Design Verification Engineer / Senior PD
时间：12-12
整理：3721RD
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Senior IC Design Verification Engineer (Sr. DV)
Requirements:
The candidate is preferred to be MSEE with minimum of 2 years, or BSEE with minimum of 4 years experience in digital ASIC/SOC design verification. The candidate should have good understanding on ASIC/SOC design flow and should have:
Good knowledge of design verification methodology, such as VMM or OVM.
Many experiences with simulation model creation and the testbench build
Strong RTL coding with Verilog and familiar with front-end design flow
Strong C/C++ software development experiences
Be familiar with scripting language, such as Perl, C shell, Makefile.
It is a plus if the candidate has one or more of the following experience/knowledge, such as X86/ARM/8051 architecture, AMBA(AXI/AHB/APB) bus, USB(3.0/2.0/1.1; SSIC/HSIC/host/device/OTG) system, NAND Flash host controller/BCH/double-data-rate interface, Universal Flash Storage, PCI-E/PCI bus, low power design, clock generation and control, SD/eMMC host controller, SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/LPC/GPIO), General connectivity IPs (I2S/I2C/UART), Ethernet, JTAG, etc.
Hands-on lab experience is another plus, able to understand and/or use the use scopes, logic analyzers, has knowledge or skill of board-level lab debugging.
The candidate is expected to exhibit good verbal and written communication skills in both Chinese and English, imaginative thinking and sophisticated analytical techniques, self-driven for quality and timely result, capability to solve complex problems and makes some modifications to standard methods and decision-making on important technical areas.
Responsibility:
The successful candidate will apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market for ASIC/SOC design. He/She should be able to work independently on various DV tasks and providing technical guidance to the DV team. The candidate would involve technically in the porting/creation of the DV environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup.
Title: Senior PD engineer
Job Description:
Work with global Front-End design team and physical design team for large scale ASIC chip physical implementation. Focus on physical design of deep sub-micron GPU chips including block level (full chip) floor planning, timing closure, place&route, physical verification etc. The individual is expected to be an expert in multiple aspects in PD areas and provide technically leadership to the engineering team. The individual is also expected to be accountable for project delivery.
Job Requirement:
3+ years or more years of experience in physical design of deep submicron digital ASIC chips
Hands on experience in large scale ASIC chip physical design
Knowledgeable in all aspects of deep submicron ASIC design flow
Successfully gone through several complete product development cycles
Demonstrate strong leadership and work well with cross-functional teams
Good listening, writing and speaking English
Good communication skills, strong interpersonal skills and the flexibility
Dedicated, hard working and good team player
Familiar with Back-End (physical design) EDA tools
Familiar with Front-End EDA tools is a plus
Familiar with Unix/Linux environment and good at scripts
This is long term project for a top IC company. We offer very competitive pay, please send your resume to careerschina@synapse-da.com if you are interested.
Requirements:
The candidate is preferred to be MSEE with minimum of 2 years, or BSEE with minimum of 4 years experience in digital ASIC/SOC design verification. The candidate should have good understanding on ASIC/SOC design flow and should have:
Good knowledge of design verification methodology, such as VMM or OVM.
Many experiences with simulation model creation and the testbench build
Strong RTL coding with Verilog and familiar with front-end design flow
Strong C/C++ software development experiences
Be familiar with scripting language, such as Perl, C shell, Makefile.
It is a plus if the candidate has one or more of the following experience/knowledge, such as X86/ARM/8051 architecture, AMBA(AXI/AHB/APB) bus, USB(3.0/2.0/1.1; SSIC/HSIC/host/device/OTG) system, NAND Flash host controller/BCH/double-data-rate interface, Universal Flash Storage, PCI-E/PCI bus, low power design, clock generation and control, SD/eMMC host controller, SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/LPC/GPIO), General connectivity IPs (I2S/I2C/UART), Ethernet, JTAG, etc.
Hands-on lab experience is another plus, able to understand and/or use the use scopes, logic analyzers, has knowledge or skill of board-level lab debugging.
The candidate is expected to exhibit good verbal and written communication skills in both Chinese and English, imaginative thinking and sophisticated analytical techniques, self-driven for quality and timely result, capability to solve complex problems and makes some modifications to standard methods and decision-making on important technical areas.
Responsibility:
The successful candidate will apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market for ASIC/SOC design. He/She should be able to work independently on various DV tasks and providing technical guidance to the DV team. The candidate would involve technically in the porting/creation of the DV environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup.
Title: Senior PD engineer
Job Description:
Work with global Front-End design team and physical design team for large scale ASIC chip physical implementation. Focus on physical design of deep sub-micron GPU chips including block level (full chip) floor planning, timing closure, place&route, physical verification etc. The individual is expected to be an expert in multiple aspects in PD areas and provide technically leadership to the engineering team. The individual is also expected to be accountable for project delivery.
Job Requirement:
3+ years or more years of experience in physical design of deep submicron digital ASIC chips
Hands on experience in large scale ASIC chip physical design
Knowledgeable in all aspects of deep submicron ASIC design flow
Successfully gone through several complete product development cycles
Demonstrate strong leadership and work well with cross-functional teams
Good listening, writing and speaking English
Good communication skills, strong interpersonal skills and the flexibility
Dedicated, hard working and good team player
Familiar with Back-End (physical design) EDA tools
Familiar with Front-End EDA tools is a plus
Familiar with Unix/Linux environment and good at scripts
This is long term project for a top IC company. We offer very competitive pay, please send your resume to careerschina@synapse-da.com if you are interested.