Sr/MTS Design Verification Engineer @深圳上海 简历发 boss@
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Sr/MTS Design Verification Engineer @深圳上海 简历发 boss@hi-talent.com
Requirements:
? The candidate is preferred to be MSEE with minimum of 2 years, or BSEE with minimum of 4 years experience in digital ASIC/SOC design verification. The candidate should have good understanding on ASIC/SOC design flow and should have:
1. Good knowledge of design verification methodology, such as VMM or OVM.
2. Many experiences with simulation model creation and the testbench build
3. Strong RTL coding with Verilog and familiar with front-end design flow
4. Strong C/C++ software development experiences
5. Be familiar with scripting language, such as Perl, C shell, Makefile.
? It is a plus if the candidate has one or more of the following experience/knowledge, such as X86/ARM/8051 architecture, AMBA(AXI/AHB/APB) bus, USB(3.0/2.0/1.1; SSIC/HSIC/host/device/OTG) system, NAND Flash host controller/BCH/double-data-rate interface, Universal Flash Storage, PCI-E/PCI bus, low power design, clock generation and control, SD/eMMC host controller, SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/LPC/GPIO), General connectivity IPs (I2S/I2C/UART), Ethernet, JTAG, etc.
? Hands-on lab experience is another plus, able to understand and/or use the use scopes, logic analyzers, has knowledge or skill of board-level lab debugging.
? The candidate is expected to exhibit good verbal and written communication skills in both Chinese and English, imaginative thinking and sophisticated analytical techniques, self-driven for quality and timely result, capability to solve complex problems and makes some modifications to standard methods and decision-making on important technical areas.
Responsibility:
? The successful candidate will apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market for ASIC/SOC design. He/She should be able to work independently on various DV tasks and providing technical guidance to the DV team. The candidate would involve technically in the porting/creation of the DV environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup.
Best Regards
Jane.Jin 金娟
Principal Consultant & General Manager @ Hi-Talent Consulting Co.,Ltd.
上海芯得企业管理咨询有限公司
上海芯相会企业管理咨询有限公司
Mob: 18502155252
E-Mail: Jane-Jin@hi-talent.com
微信： xinde_jane
QQ: 1600548210
Weibo: http://weibo.com/u/1716864892
webside： www.hi-talent.cn
Requirements:
? The candidate is preferred to be MSEE with minimum of 2 years, or BSEE with minimum of 4 years experience in digital ASIC/SOC design verification. The candidate should have good understanding on ASIC/SOC design flow and should have:
1. Good knowledge of design verification methodology, such as VMM or OVM.
2. Many experiences with simulation model creation and the testbench build
3. Strong RTL coding with Verilog and familiar with front-end design flow
4. Strong C/C++ software development experiences
5. Be familiar with scripting language, such as Perl, C shell, Makefile.
? It is a plus if the candidate has one or more of the following experience/knowledge, such as X86/ARM/8051 architecture, AMBA(AXI/AHB/APB) bus, USB(3.0/2.0/1.1; SSIC/HSIC/host/device/OTG) system, NAND Flash host controller/BCH/double-data-rate interface, Universal Flash Storage, PCI-E/PCI bus, low power design, clock generation and control, SD/eMMC host controller, SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/LPC/GPIO), General connectivity IPs (I2S/I2C/UART), Ethernet, JTAG, etc.
? Hands-on lab experience is another plus, able to understand and/or use the use scopes, logic analyzers, has knowledge or skill of board-level lab debugging.
? The candidate is expected to exhibit good verbal and written communication skills in both Chinese and English, imaginative thinking and sophisticated analytical techniques, self-driven for quality and timely result, capability to solve complex problems and makes some modifications to standard methods and decision-making on important technical areas.
Responsibility:
? The successful candidate will apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market for ASIC/SOC design. He/She should be able to work independently on various DV tasks and providing technical guidance to the DV team. The candidate would involve technically in the porting/creation of the DV environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup.
Best Regards
Jane.Jin 金娟
Principal Consultant & General Manager @ Hi-Talent Consulting Co.,Ltd.
上海芯得企业管理咨询有限公司
上海芯相会企业管理咨询有限公司
Mob: 18502155252
E-Mail: Jane-Jin@hi-talent.com
微信： xinde_jane
QQ: 1600548210
Weibo: http://weibo.com/u/1716864892
webside： www.hi-talent.cn
典型的AMD啊
AMD哪有在深圳做IC的？