soc总监和数字经理-芯得20151118

Position: Senior Manager or Director, depending upon qualification, of SOC Design
简历发 offer@hi-talent.net  
Job Description:
(1)   Lead a SOC design team that includes IC architecture, logic design, integration, verification, and validation.
(2)   Provide technical consultation and resolve technical issues on product development.
(3)   Work with MKT for product definition, SE for system design, SW for verification and validation
(4)   Lead tasks related to IC production, including issue debugging, bug fix, and solution.
Job Requirement
o      Fluent in Verilog, Familiar with System Verilog and/or System C
o      Familiar with C language. Knowledge of scripting languages is a plus.
o      Intimate knowledge on SOC architecture
o      Familiar with RISC architecture and bus protocols such as AXI and AHB
o      Intimate knowledge on bus arbitration for SOC design
o      Familiar with FPGA prototype verification flow
o      Knowledge of SOC peripheral modules such as flash controller, DDR controller, AV interfaces (HDMI, CVBS, YPbPr, I2S, S/PDIF)
o      Knowledge of audio and video technology
o      Experience on large-scale emulator system (Veloce and/or Palladium)
o      Master degree with at least 10 years of IC development experience
o      Successful IC tape-out in 40 nm or more advanced processes
o      Proven track record of large-scale SOC production
Senior Digital Manager 简历发 offer@hi-talent.net
Job description:
- Conduct technical feasibility analysis,  define chip micron architecture and module spec’s;
- Work with analog design lead for new product development project planning and tracking;
- Design, implementation, and verification of digital in mixed-signal ICs;
- Perform backend digital design (logic synthesis, formal check, define design constraints for place and route, perform timing closure, DFT)
- Script based synthesis & timing analysis on GHz working frequency
- Support system, test and product team with chip debugging, failure analysis, characterizations and product release efforts
Requirements:
- PH.D or MSEE with minimum 10-year design and project lead experience of mixed-signal chip development experience
- Solid knowledge and design experience in very high speed SoC with embedded MPU
- Projects tape out experience with 65nm process, 40nm or 28nm
- Relevant experience on DDR/Serdes interface is a plus
- Solid knowledge of high-speed synchronous/asynchronous circuit design, family with standard cell architecture and behavior
- Family with low-power-design flow and techniques
- Strong skills of Verilog RTL coding, verification and debug
- Hands on experience in EDA tools such as Cadence NC-Sim, Synopsys DC, PT, etc.
- Solid knowledge of documentation of design report
- Highly organized and self motivated
- Ability to plan and  manage a project and effectively drive team’s execution
Best Regards
Jane.Jin 金娟
Principal Consultant & General Manager @ Hi-Talent Consulting Co.,Ltd.
上海芯得企业管理咨询有限公司
上海芯相会企业管理咨询有限公司
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