高级数字设计经理
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职位：高级数字设计经理@上海 北京
简历发 芯得爱德华 offer@hi-talent.net
JOB DESCRIPTION:
- Conduct technical feasibility analysis, define chip micron architecture and module spec’s;
- Work with analog design lead for new product development project planning and tracking;
- Design, implementation, and verification of digital in mixed-signal ICs;
- Perform backend digital design (logic synthesis, formal check, define design constraints for place and route, perform timing closure, DFT)
- Script based synthesis & timing analysis on GHz working frequency
- Support system, test and product team with chip debugging, failure analysis, characterizations and product release efforts
QUALIFICATION:
- PH.D or MSEE with minimum 10-year design and project lead experience of mixed-signal chip development experience
- Solid knowledge and design experience in very high speed SoC with embedded MPU
- Projects tape out experience with 65nm process, 40nm or 28nm
- Relevant experience on DDR/Serdes interface is a plus
- Solid knowledge of high-speed synchronous/asynchronous circuit design, family with standard cell architecture and behavior
- Family with low-power-design flow and techniques
- Strong skills of Verilog RTL coding, verification and debug
- Hands on experience in EDA tools such as Cadence NC-Sim, Synopsys DC, PT, etc.
- Solid knowledge of documentation of design report
- Highly organized and self motivated
- Ability to plan and manage a project and effectively drive team’s execution
Best Regards
Jane.Jin 金娟
Principal Consultant & General Manager @ Hi-Talent Consulting Co.,Ltd.
上海芯得企业管理咨询有限公司
上海芯相会企业管理咨询有限公司
Mob: 18502155252
E-Mail: Jane-Jin@hi-talent.com
微信： xinde_jane
QQ: 1600548210
Weibo: http://weibo.com/u/1716864892
webside： www.hi-talent.cn
简历发 芯得爱德华 offer@hi-talent.net
JOB DESCRIPTION:
- Conduct technical feasibility analysis, define chip micron architecture and module spec’s;
- Work with analog design lead for new product development project planning and tracking;
- Design, implementation, and verification of digital in mixed-signal ICs;
- Perform backend digital design (logic synthesis, formal check, define design constraints for place and route, perform timing closure, DFT)
- Script based synthesis & timing analysis on GHz working frequency
- Support system, test and product team with chip debugging, failure analysis, characterizations and product release efforts
QUALIFICATION:
- PH.D or MSEE with minimum 10-year design and project lead experience of mixed-signal chip development experience
- Solid knowledge and design experience in very high speed SoC with embedded MPU
- Projects tape out experience with 65nm process, 40nm or 28nm
- Relevant experience on DDR/Serdes interface is a plus
- Solid knowledge of high-speed synchronous/asynchronous circuit design, family with standard cell architecture and behavior
- Family with low-power-design flow and techniques
- Strong skills of Verilog RTL coding, verification and debug
- Hands on experience in EDA tools such as Cadence NC-Sim, Synopsys DC, PT, etc.
- Solid knowledge of documentation of design report
- Highly organized and self motivated
- Ability to plan and manage a project and effectively drive team’s execution
Best Regards
Jane.Jin 金娟
Principal Consultant & General Manager @ Hi-Talent Consulting Co.,Ltd.
上海芯得企业管理咨询有限公司
上海芯相会企业管理咨询有限公司
Mob: 18502155252
E-Mail: Jane-Jin@hi-talent.com
微信： xinde_jane
QQ: 1600548210
Weibo: http://weibo.com/u/1716864892
webside： www.hi-talent.cn
多少钱！
够直接。。。