Xeon Haswell的一些技术细节
时间：12-12
整理：3721RD
点击：
- 18x Haswell cores (max), 45 MB cache in 2 rings, 40x QPI (9.6 Gt/s) Lanes, 40x PCIe (8 Gt/s) Lanes, 4x 1067 MHz DDR4
- double-error-correct, triple-detect in cache
- 22 nm FinFET, 11 metal layers, 5.69 Gxter in 662 mm2
- 33% perf gain average over family
- The integrated voltage regulators use 183 inductors. Have planar L in center and vertical near pins to reduce coupling.
- FIFOs to cross power/clock domain. Tried to minimize level shifters
- Can test to find which of 8 curves of V vs F a die matches, and program that in.
- More sophisticated turbo mode (over-voltage): do per core and look to see if a core is stalling a lot and downrate it.
- FIVR saves cost by reduction of off-chip regulators, saving in pins, savings in package substrate size (fewer pins), offset by die size increase, but net win.
- Parity or ECC on all reg files and SRAMs. FIVR control particularly protected.
- 10 pJ/bit on high-speed serdes
- double-error-correct, triple-detect in cache
- 22 nm FinFET, 11 metal layers, 5.69 Gxter in 662 mm2
- 33% perf gain average over family
- The integrated voltage regulators use 183 inductors. Have planar L in center and vertical near pins to reduce coupling.
- FIFOs to cross power/clock domain. Tried to minimize level shifters
- Can test to find which of 8 curves of V vs F a die matches, and program that in.
- More sophisticated turbo mode (over-voltage): do per core and look to see if a core is stalling a lot and downrate it.
- FIVR saves cost by reduction of off-chip regulators, saving in pins, savings in package substrate size (fewer pins), offset by die size increase, but net win.
- Parity or ECC on all reg files and SRAMs. FIVR control particularly protected.
- 10 pJ/bit on high-speed serdes
FIVR是啥，F integrated voltage regulator？
嗯，Fully Integrated Voltage Regulator
22nm,这么落后的工艺？