Cadence内推AE/PE/RD/SoC 上海/北京/深圳 职位
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masking (马斯金) 于 (Thu Nov 1 19:46:09 2012) 提到:
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英文简历发送至 xiny@cadence.com 注明职位。
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Shanghai R&D Vacancies (Nov. 2012) RD, PE, PV & Internship
R&D
1. Senior Software Engineer for Encounter Hier Solution Team (Req#:
6638)
Position Description
The candidate will be a member of the Encounter Hier Solution
team in Shanghai, to work on the development and maintenance of
Hier Solution project.
The responsibilities include development of new features and
products, and support other teams in Encounter product lines.
The candidate must be comfortable working with existing code as
well as developing new functionality to address new requirements,
and be working closely with local/remote team members, and be also
strong technical support to team.
Position Requirements
Candidate must be an expert in software engineering methods and
committed to high quality of development work.
The individual must be team-oriented, possess good communication
skills, self-motivated, able to work independently and working with
a team from multiple remote sites.
Candidate must be able to develop detailed technical
specification as well as the ability to scope efforts required.
The candidate must be also smart to capture new EDA technologies,
and switch among different areas successfully.
Advanced developing and debugging software in UNIX & LINUX
environments, familiar with gnu c/c++, gdb etc..
Strong problem-solving, architecture, algorithmic.
Familiar with interpreted language such as TCL is a plus.
Knowledge of Timing analysis is a plus。
2. Senior Software Engineer for EDI IPO (Req#: 7035, 7036, 7037,
7038, 7039)
Position Description
Working on EDI IPO function on CCR fixing, memory and performance
profiling as well as new enhancements.
Position Requirements
MS/PHD from computer science, EE, math or related
The candidate must be also smart to capture new EDA technologies,
and switch among different areas successfully.
Strong problem-solving, architecture, algorithmic.
Familiar with interpreted language such as TCL is a plus.
3. Senior Product Engineer (Req#: 6934)
Position Description
As a Product Engineer for Cadence’s Encounter Test product group,
you’ll have the opportunity to apply your academic background and
project based experience to the challenge of enabling our customers
to utilize our key test technologies such as Design-For-Test (DFT)
structures, Automatic-Test-Pattern-Generation (ATPG), and
Diagnostics. Your challenge will be to make our customers
successful in meeting their test cost and quality metrics, using
the leading-edge tools in the Encounter Test product family.
Through your training period, you’ll be mentored by a senior team
member with years of industry experience in test, and you’ll have
the opportunity to differentiate yourself by bringing your unique
skills to the challenge. Our customers consist of many of the
leading chip design teams in the industry, and they’ll count on you
for your expertise in enabling them to test their critical products
in an effective manner.
If you’re looking for a challenging work environment, as part of a
fast paced, close-knit, and technologically advanced team, then we’
re looking for you.
Other responsibilities of the product engineering position
include:
Interfacing and working with directly R&D
Interfacing directly with field application engineers and
customers
Supporting and debugging customer test design methodologies using
our products
Optimizing product documentation, application notes, videos,
training and demos to facilitate product adoption
Enhancing product usability by both advocating for product
changes, and improving product support collateral
Position Requirements
MSEE/MSCE required
2-4 years of related industry experience
Excellent communication skills (written and verbal)
Strong programming and scripting skills
Strong group presentation skills
Familiarity with Test fundamentals (DFT, ATPG and Diagnostics
concepts)
Coursework and/or project-based experience dealing with the
digital design process
Experience with Cadence or other EDA/test tools a plus
Good command of the English language, both written and spoken –
Required
4. Software Engineer for Memory Modeling (Req#: 6958)
Position Description
Responsible for designing and developing models of system level
memories like DDR SDRAM, NAND Flash, EEPROM and eMMC for use on
hardware based verification products.
In addition modifying, updating, maintaining and productizing
existing system level memory model products.
Perform as individual contributor involving RTL design,
verification, productizing and documentation.
Work on moderately complex problems related to emulation,
simulation or verification issues.
Position Requirements
The position requires BSEE, or equivalent, with a minimum of 2
yrs of industry experience in designing hardware systems.
Must have excellent communication skills, both written and
verbal.
RTL design knowledge using Verilog is required along with
experience in using RTL verification tools and flows.
In addition Verification using Cadence simulation products is
desired as is Verification experience using emulation products.
Experience with scripting languages like Perl, TCL C-shell is
strongly recommended.
5. Senior Software Engineer for HDL Compiler (Req#: 6933)
Position Description
Responsible for designing, developing, troubleshooting and
debugging software programs on Linux/Unix platforms.
Develops electronic design automation (EDA) software tools
involving RTL synthesis, hardware emulation and design
verification.
Works on complex problems where analysis of situations or data
requires an in-depth evaluation of various factors.
Exercises judgment within broadly defined practices and policies
in selecting methods, techniques, and evaluation criteria for
obtaining results.
Utilizes and integrates various EDA tools for synthesis,
simulation, verification acceleration, and formal verification.
Works together with an R&D group in Silicon Valley of the United
States.
Position Requirements
MS in EE/CS required. Pd.D. in EE/CS preferred.
Proficiency in English reading and writing.
Proficiency in C++/C programming on Linux platform.
Knowledge in digital IC design.
Knowledge in Verilog, VHDL, or SystemVerilog.
Knowledge in logic synthesis, simulation, formal verification, or
emulation preferred.
6. Senior Software Engineer for CTS
Position Description
The primary responsibility is designing, developing,
troubleshooting and debugging software programs on Unix/Linux
platforms. Will be involved in CTS development for Encounter.
Position Requirements
MS in EE/CS with 2+ years or PhD in EE/CS
Strong physical design (EDA) background (Digital IC)
Excellent programming skills (C/C++, script)
Good written and spoken English
Good communication skills and be able to work both independently
and in a team.
R&D engineer to do the clock tree/mesh synthesis related works
(software development, design flow improvement)
PE
1. Product Engineer for GUI and usability (Req#: 6846)
Position Description
Work on Encounter Digital Implementation system Graphic User
Interface features.
Understand and define customer requirements. Work with RD and
global cross-function-team to ensure the development can fulfill
customer requirements and methodology.
Position Requirements
Master degree and majored in EE/CS/EDA
Familiar with IC physical design flow
with GUI and usability sense for user interaction
Fluent English in both oral and written
2. Principal Product Engineer for Cadence PDK (Req#: 7032)
Position Description:
Work in Cadence Foundry Access Team based in Shanghai. Major
responsibilities include:
To provide key technical support in Cadence PDK implementation
for our foundry partners in Shanghai;
Support customers in Cadence PDK application thru whole Cadence
Custom IC design flow
In charge of Custom IC reference flow development.
Position Requirements:
A bachelor's degree is essential and 9+ years experience, or
master's degree with 7+ years experiences in PDK development or
Custom IC design flow applications.
Strong scripting capability, including Skill/Shell/Perl.
Expertise in Custom IC data format, including CDF, PCell, CDL,
GDSII, av_extracted view, Virtuoso techfile, etc.
Familiar with Cadence CIC tools, including IC5141/IC61 platform,
Spectre, AMS designer, Assura, QRC, etc.
Ability to understand and articulate technical issues, (and
knowledge of) design products and their applications.
Good communication in English and Chinese, team spirit, self-
confidence and self-motivation.
Internship
1. PV Intern for GPS (Global Physical Synthesis) (Req#: 7033)
Position description
This intern will work in ICD (P&R) Product Validation team. The
responsibilities include:
Assist in Cadence GPS product and engine's development and
validation
Validate comprehensive GPS test cases for Encounter Digital
Implementation System
Develop and maintain system and infrastructure for high
productivity and efficiency with various scripting and system
development techniques
Position Requirements
MS or excellent undergraduate, Strong perl programming
experience.
IC design knowledge is necessary, statistic timing analysis
knowledge is a strong plus
Unix System knowledge, vi/TCL/TK/CSH will be plus.
Good communication in English and Chinese, good confidence and
good self-motivation.
2. PV Interns - System and Regression(Req#: 7084)
Position description
Need 4 days/week or full time working with PV regression team for
system enhancement
Help PV team on scripts development.
Position Requirements
MS or excellent undergraduate, Strong perl programming
experience.
IC design knowledge is necessary, such as statistic timing
analysis
Unix System knowledge, vi/TCL/TK/CSH will be plus.
Good communication in English and Chinese, good confidence and
good self-motivation.
3. PV Intern for STA (Static Timing Analysis)
Position description
This intern will work in Encounter Common Timing Engine Product
Validation team. The responsibilities include:
Assist in Cadence STA product and engine's developement and
validation
validate comprehensive STA testcases for Encounter Digital
Impelementation System and Encoutner Tming System
Develope and maintain system and infrastructure for high
productivity and efficiency with various scripting and system
developement techniques
Position Requirements
MS or excellent undergraduate
Digital IC design knowledge is necessary, statistic timing
analysis knowledge is a strong plus
Unix System knowledge, vi/TCL/TK/CSH/Perl will be plus.
Good communication in English and Chinese, good confidence and
self-motivation.
Commitment to work as intern for at least 6 months
Beijing RD & PE Vacancies (Nov.2012)
R&D
1. Member of consulting staff for Cadence Virtuoso Environment
(Location:BJ) ( Req#: 6332)
Position Description
The Cadence Virtuoso platform powers all of the latest design
innovations in consumer, mobile and enterprise electronics
worldwide. We are looking for an exceptional senior software
engineer to join our team and contribute to the continued growth
and success of the company’s flagship product. In this high-impact
career opportunity, you will lead design and development of
cutting-edge features of some of our most exciting new products,
with an emphasis on circuit simulator integration in the Virtuoso
ADE/ADE XL environment. You will contribute both individually and
as a technical lead, working with a cross-functional team in
Beijing and San Jose to ensure that our software is developed,
tested, and documented with high quality.
Position Requirements
Exceptional C++ programming and familiarity with Linux/Unix
development.
Experience with GUI frameworks, such as Qt.
Strong scripting language skills in one or more of: Python, Perl,
Lisp, Tcl.
Proficiency with build and version-control systems.
Excellent written and oral English communication skills.
Coursework or work experience in electronic circuit design.
Exposure to the Cadence Virtuoso environment or other electronic
design platforms.
B.S. in engineering, computer science or related field. Graduate
degree preferred.
2. Senior Member of Technical Staff, Simulation Integration
(Location:BJ) ( Req#: 6937)
Position Description
World’s leading design companies rely on Cadence technologies to
deliver the latest design innovations in consumer, mobile and
enterprise electronics. We are looking for exceptional software
engineers to join our team and contribute to the continued growth
and success of the company’s flagship products, such as Virtuoso
Spectre and Virtuoso ADE. In this high-impact career opportunity,
you will develop cutting-edge features of some of our most exciting
new products, with an emphasis of scripting language development
and GUI integration. You will work with a cross-functional team in
Beijing and San Jose to ensure that our software is developed,
tested, and documented with high quality.
Position Requirements
Strong C++ programming and familiarity with development under
Linux/Unix environment.
Proficiency with linux/unix tools.
Skills in one or more of script such as Python, Perl.
Familiar with build and version-control systems.
Good English communication skill both verbally and writing.
Good problem solving skill and team work spirit.
Preferred Skills
Experience in the use of parser generators, such as Antlr or
Yacc/Lex
Exposure to circuit simulators, such as SPICE, HSPICE and
Spectre.
Coursework or work experience in analog or mixed-signal circuit
design
Education
EE, computer science or related field.
3. Member of Technical Staff-Virtuoso ADE XL software
developer(Location:BJ) ( Req#: 5918)
Position Description
Custom digital and analog circuit designers must generate and
interpret large amounts of complex simulation data. Virtuoso ADE XL
accelerates design by enabling setup reuse, parallelizing compute-
intensive simulation, and through extensive post-processing and
visualization capabilities. We are seeking a talented software
developer to improve simulation throughput and data visualization.
Position Requirements
Demonstrated proficiency in C++ and general software development
skills
BS in Computer Science or Computer Engineering required.
XML, SQL, GUI (Qt specifically), and distributed processing
experience a plus.
Experience with Cadence Virtuoso or analog circuit design is a
plus.
4. Member of Consulting Staff (Location:BJ) ( Req#:6158)
Position Description
The position is for analog circuit simulation engineer
responsible for designing, implementing and maintaining device
compact models in SPICE-like circuit simulation software for use
with analog, RF and mixed signal circuit simulators. The engineer
will be responsible for leading multiple development efforts
through the development process, including writing specifications
based on marketing and product requirements, designing and
implementing product improvements and fixes, and working with a
cross-functional team to ensure the software is tested, integrated
and documented. The engineer must be proficient in C/C++ Unix
development, and have a thorough knowledge of device physics,
device compact models. The engineer must have a proven ability to
learn from and work with an engineering and cross-functional team
to deliver innovative products in a production environment.
Position Requirements
Well devices physics, device compact models;
Familiar with matrix solver & mathematic calculation;
Familiar with Spice, Spectre format & usage;
Skilled in C++ programming, familiar with development under
Linux/Unix environment;
Be familiar with Analog-signal design is a plus;
Good English communication skill both verbally and writing;
Good problem solving skill and team work spirit;
5. Senior member of technical staff - Characterization RD
(Location: BJ) ( Req#:5879)
Position Description
The positions are for a developer who will be responsible for
designing, implementing, and maintaining library characterization
and validation software for use with standard cells, memory and
macro blocks, and IO cells.
Position Requirements:
The candidates should have two or more years of experiences in
developing EDA software.
Must be proficient in C, C++, TCL, and development in Linux/Unix.
Knowledge on semiconductor device is strong plus.
Experience with SPICE or SPICE-like circuit simulation is
important.
Knowledge of Verilog and VHDL is also highly desirable.
Have a good understanding of library characterization, IP design,
static timing analysis, power analysis, and signal integrity
analysis flows.
Minimum Education Required / Minimum Experience Required : MS,
EE, CS, Math or Physics 2
Preferred Education / Preferred Experience: Ph.D. , EE, CS, Math
or Physics 3-5
6. Senior member of technique staff for Verilog-A simulator
development (Location: BJ) ( Req#:7098)
Position Description:
Develop, enhance and maintain Verilog-A simulator.
Position Requirements:
Familiar with Spice, Verilog-A, Verilog-AMS language
Skilled in C++ programming, familiar with development under
Linux/Unix environment.
Analog circuit or digital simulator development experiences.
Well understanding on circuit simulation technology, including
MNA, dc, tran method.
Good mathematic background & knowledge.
Be familiar with Analog Mixed-signal design is a plus
EE or CS Master degree with at least 2 years related working
experience or above
PE
1. Senior Product Engineer – Characterization (Location: BJ)
(Req#:5546)
Position Description
The Altos Product Engineer (PE) works with key customers to
understand their library characterization challenges, maps
Customer needs into product requirements, and collaborate with
the R&D and PV organization to ensure that the product
Implementation addresses the customer’s real needs.
The Altos PE plays a pivotal role in defining and deploying
Cadence’s library characterization products and solutions at key
customers that enable them to do characterization at a very high
performance & efficiency.
This position requires problem discovery and analysis at customer
site, assessment of possible solutions, collaborating with RD and
customer to develop and test the solution, and managing it’s
deployment at the customer site.
Position Requirements:
The candidate should possess minimum a Bachelors technical degree
and 3-5 years of industry experience
Minimum 3 years hands-on, expertise on library characterization,
IP design, static timing analysis, power analysis, and signal
integrity analysis flows.
Hands on Design experience using Verilog, VHDL
Experience with SPICE or SPICE-like circuit simulation is strong
plus
Knowledge on semiconductor device is strong plus.
Knowledge on competitor characterization flow and tools is a plus
Highly technical & hands on engineer with an ability to partner
with key customers and provide expert support to field application
engineers.
The candidate must be able to drive R&D and Application engineers
and have passion to make customers successful.
She/he must be willing to travel worldwide in order to work
closely with customers in any part of the world.
Passionate about adopting and promoting new technologies and
making customers successful.
Successful in building and delivering training content on rolling
out new products/methodologies
Very good communication skills and a strong desire for working in
a global environment with customers Developers, marketing and
sales.
English fluency is a must, Korean speaking language is a plus
AE & Solution Engineer Vacancies (Nov. 2012)
1. Lead/Principle Application Engineer – ICD backend support
(Location: BJ/SH)
(Req #: 6835, 6836)
Position Description:
To provide key technical support in digital IC design
implementation, product demonstration, and sales presentations.
To demonstrate strong ability and to be hands-on in RTL-to-GDSII
design methodology, for challenging low power designs, for 200MHz
to several GHz big chips.
Have real design experience including conformal check, logic
synthesys, P&R, CTS, SSTA, MMMC to close timing, power and die
area.
Assist in technical evaluation, assessment and delivery of
concurrent ASIC/SoC designs. To play a leading role among other
team members, while receive little instruction on routine and
general assignments.
Position Requirements:
Bachelor's degree with 7+ years experience in IC design, majoring
in electronic engineering or computer science applications.
Mater degree and/or working experience in multi-nation IC design
house is preferred.
Ability to understand and articulate technical issues, (and
knowledge of) design products and their applications.
Requires working knowledge of one or more programming languages,
and effective communication and soft skills
3. Lead Application Engineer AMS (Location: SH) (Req #:6762)
Position Description:
Provide technical support for Cadence Custom IC front to back
design flow. Mainly focus on analog/RF/mixed-signal circuit
simulation products support.
Has thorough understanding of Cadence Virtuoso solution
marketplace and objectives, including key players, products and
trends.
Support sale to address customers' technical demand to propose
and deliver value position for maximizing business opportunities.
Conduct Cadence Virtuoso products demonstration, presentation,
workshop and benchmark to address the customer's technical
concerns.
Provide post-sales support such as products training, software
environment maintain, products usage guide to assure customer
satisfaction and nurture future sales potentials.
Ability to openly exchange and communicate technical information
with peers, group management, and customers.
Position Requirements:
Bachelor's degree majoring in electronic engineering or computer
science applications, with 5+ years experience in Analog and RF IC
design.
Mater degree and/or working experience in multi-nation IC design
house is preferred.
Strong verbal and written skills in English are required.
Have good communication skill and teamwork spirit.
4. Lead Application Engineer (Location: SH) (Req # 6765)
Position Description:
Work closely with the Sales team to identify and scope
opportunities for Cadence Emulation and Acceleration products.
Plan, execute and manage key technical evaluations and benchmark
with existing and potential customers.
Train, ramp-up and accompany customer project.
Conduct basic and advanced trainings, presentations and demos as
necessary.
Providing technical expertise to address clients’ queries, which
need expert involvement.
Aligned closely with corporate engineering and sales/marketing
team on customer requirement for product direction/improvement.
Position Requirements:
4~6 years experience in the following areas:
HW verification with knowledge of System Verilog/VHDL and HDL
simulators
FPGA prototyping project experience is a must
Experience with hardware emulator or accelerator is a big
advantage
Advanced Verification Methodology like OVM or VMM is a plus
Knowledge of UNIX and Linux is highly desired
Strong verbal and written communication skills in English
Strong teamwork skills with good human relationship
5. Technical Lead/ Lead Service Engineer of methodology group
(Location:
BJ/SH/SZ) (Req #:6734, 6735, 6736)
Position Description
This position requires excellent design experiences in the
digital implementation domain including Floorplan, P&R, STA,
Physical verification, DFM.
Must have a solid background in circuits, electronics & physics &
should be very willing to learn new stuff.
Responsible for large sized design implementation tasks &
architectural tasks, which requires ability to assess Customer's
Design environment, to understand his application needs & to build
new Design environment based on specifications & available Cadence
tool technology.
Ability to acquire a basic understanding of the (services)
business environment of Cadence within 1 month. Feeling responsible
for technical delivery as well as business development &
opportunity creation.
Behavioral competencies: Teamwork; Customer focus;
Accountability; Communication; Coaching & feedback; Leadership
Position Requirements:
MS degree with 10+/7+ years of applicable experience in
electrical engineering, microelectronics.
Essential that the individual demonstrates strong communication,
verbal and written, and project management skills.
Good verbal and written communication skill in English is needed.
Will have demonstrated hands-on experience and expertise with
Cadence logical and physical design tools (SoC Encounter,
Conformal, QRC, Vstorm, ETS/CNDC, and PVS) or equivalent tools,
flows and methodologies required to execute a physical design
project.
Will have demonstrated successful completion of 5+ physical chip
implementation projects through to tape (better to have 65nm or
hierarchical implementation experience) as an individual
contributor
Will have demonstrated successful completion of at least ten
physical design projects as a technical leader.
Able to work on-site at customer premises, travel up to 30%, and
put in long hours when required to meet customer deadline.
Experience in sign-off tools for STA, IR drop, power analysis, SI
analysis is a plus
Knowledge and experience in design for advanced process nodes
(40nm and below) is a plus.
6. Principle Solution Engineer – Verification
Position Description
The Incisive Solution Engineer works with key customers to
understand their design and verification challenges,
Collaborate with the R&D and PV organization to ensure that the
product implementation addresses the customers’ real needs.
The Solution Engineer plays a pivotal role in defining and
deploying Cadence’s Incisive Simulator products
and solutions at key customers to enables them to do functional
verification at a very high performance & efficiency.
This position requires problem discovery and analysis at customer
site, assessment of possible solutions,
Collaborating with R&D and customer to develop and test the
solution, and manage the deployment at the customer site.
The position also requires mentoring junior application engineers
on verification solutions and tool usage.
The position requires 100% presence in Asia Pacific area.
Position Requirements
The candidate should possess minimum a Bachelors technical degree
and 5-8 years of industry experience
- Minimum 5 years hands-on, expertise on simulation based design &
verification techniques.
- Hands on experience using HDL simulator is a must
- Knowledge on competitor verification flow and tools is a plus
- Hands on Verification experience using
SystemVerilog/e/SystemC/Vera
- Hands on Design experience using Verilog, VHDL, SystemC
- Hands-on experience optimizing RTL and Gate-level simulation to
improve performance is a plus
- Ability to partner with key customers and provide expert support
to field application engineers
The candidate must be able to drive R&D and Application engineers
and have passion to make customers successful
- Must be willing to travel worldwide in order to work closely with
customers in any part of the world
- Highly organized individual with demonstrated ability to handle
multi-task activities and projects
- Passionate about adopting and promoting new technologies and
making customers successful
- Building and delivering training content to roll out new solution
and methodologies
- Very good communication skills
- English fluency is a must, Chinese and/or Korean speaking
language is a plus
- Multi-years working experience with western companies (EMEA or
USA) is a plus
- Experience to lead projects and people will be strongly taken
into consideration
SoCR Vacancies – Nov 2012 (SH & BJ)
1. Lead Physical Design Engineer (Location: SH) (Req #: 6745)
Position Description:
Perform physical design implementation, including synthesis,
floor planning, power grid design, place and route, clock tree
synthesis, timing closure, power/signal integrity signoff, physical
verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure, and
physical design project management.
The candidate will have the opportunity to work on many varieties
of challenging designs, i.e. low power and high speed design. The
responsibility includes participating in or leading next generation
physical design, methodology and flow development.
Position Requirements:
BS degree with 10+ years of applicable experience, MS degree with
7+ years of applicable experience in electrical engineering,
microelectronics. Experienced with ASIC design flow, hierarchical
physical design strategies, and methodologies and understand deep
sub-micron technology issues.
Solid knowledge on LP Design, DFT, static timing analysis, EM/IR-
Drop/crosstalk analysis, formal verification, physical
verification, DFM.
Successful track records of taping out complex, 65/40/28 nm SOC
chips.
Automation and programming-minded, solid coding experience in
Makefile/Tcl/Tk/Perl.
Self-motivated, able to work independently or as a team player,
excellent verbal and written communication skills in English.
2. Lead Implementation design Services Engineer (Location: SH) (Req
#:6662)
Position Description:
The candidates should be senior in a way that they are not only
technical excellent but also mature & able to communicate with
customers, following team members. This engineer should have
excellent design experiences in the digital implementation domain
including Floor plan, P&R, STA, Physical verification, DFM. The
engineer must have a solid background in circuits, electronics &
physics & should be very willing to learn new stuff.
Position Requirements:
Ability to handle large sized design implementation tasks &
architectural tasks alone.
Ability to assess Customer's Design environment, to understand
his application needs & to build new Design environment based on
specifications & available Cadence tool technology.
Ability to acquire a basic understanding of the (services)
business environment of Cadence within 1 month.
Working on multi person projects of varying complexity, working
especially in a multi-site/multi-cultural project.
The latter requires good communication skills in English.
Feeling responsible for technical delivery as well as business
development & opportunity creation.
Behavioral competencies: Teamwork; Customer focus;
Accountability; Communication; Coaching & feedback; Employee
development; Leadership.
3. Principle Design Engineer – SoC Architecture & Algorithm
(Location: SH)
Position Description:
In charge of SoC Spec definition, chip or complex IP architecture
design. The engineer should be able to leading projects and
initiatives. Exercise judgment within generally defined practices
and policies.
Algorithm study, modeling and verification.
Specific duties include: - Be responsible for the design micro-
architecture, system and test platform development - Proficiency in
logic design, simulation - Proficiency in Verilog and its
simulation environment -At least six years experience on driving
complex IC development projects on wired/wireless telecom and high
speed interface, excellent communication skills and the uncanny
ability to both lead and contribute in a cooperative team
environment is required.
Position Requirements:
Have BS degree with 12+ years of applicable experience, MS degree
with 10+ years of applicable experience or PhD degree with 6+ years
of applicable experience in architecture and system. Candidate must
have experience on mass product and hands on hardware verification
Strong knowledge with DSP and mixed signal design in Digital
communication, DTV or Multimedia.
Must have strong Mathematics skill. Knowledge of Matlab, or
C/C++, or System C, SystemVerilog or Verilog is necessary.
Experience of DSP based Architecture design. Good Knowledge of
CPU, DSP and GPU.
Good knowledge on wired high-speed interface standard
Ability to work effectively alone or as well as in a team.
Essential that the individual demonstrates strong communication,
verbal and written
Requires good communication skills in English.
4. Staff/Principal SerDes Analog IC Design Engineer (Location: SH)
(Req #:6662)
Position Description:
Responsible for the design and development of SerDes analog/mixed
signal IC circuit blocks from initial concept and specification
through final verification and conformance to customer
requirements.
Candidate’s background should demonstrate good problem solving
skills, excellent analog aptitude, good communication skills, and
ability to work cooperatively in a team environment.
Must have demonstrated experience in SerDes transceiver designs
including some of the following circuit blocks: System level
modeling by matlab, C, or VerilogA; Driver; Receiver; Serializer;
Deserializer; Phase Interpolator; Low jitter PLL; High Speed Clock
Distribution; Bias and Bandgap; Voltage Regulators.
Have working knowledge of a set of common SerDes standards and
their electrical requirements, and a thorough understanding of
jitter.
Requires proficiency in using CAD tools for circuit simulation,
layout, and physical verification (Cadence tool experience, lab
test experience, and experience at 65nm and below technologies are
a plus).
Job Requirements:
BSEE [MSEE/Ph.D EE preferred]
Minimum 8 years experience in CMOS SerDes IC design
5. Design Engineer – Analog circuit (Location: SH) - campus
recruitment
(Req #: 7086, 7087)
Position Description:
In charge of analog and mixed-signal circuit design.
Hands-on experience conducting design analysis and recommending
appropriate solutions
Architecture study, modeling and verification.
Specific duties include: - Analog circuit simulation, layout
guidance, test chip measurement and debug
Excellent analytical and problem-solving skills. Quick learner-
able to learn and apply technical and complex topics.
Excellent communication skills and the uncanny ability in a
cooperative team environment are required.
Self-motivated, result-oriented, can take ownership and follow-
through on tasks.
Position Requirements:
Essential Qualifications:
Master or PHD degree, major in Micro-Electronics, Electronic
Engineering or equivalent
Ability to work effectively alone or as well as in a team.
Essential that the individual demonstrates strong communication,
verbal and written
Requires good communication skills in English. Desirable
Qualifications:
Knowledge of one of key Analog IC design areas and their
architectures/applications: Data Converters; PLL's; Oscillators;
Low Noise Design; RF IC building blocks
Solid understanding of IC design technology and
process/methodology in IC design solutions
Familiar with Cadence analog and mixed-signal EDA tools is a plus
6. Design Engineer – Algorithm & Architecture (Location: SH) -
campus recruitment
(Req #: 7071)
Position Description:
In charge of SoC Spec definition, whole chip or complex IP
architecture design.
Algorithm study, modeling and verification.
Specific duties include: - Owning the IC micro-architecture,
package and test platform development - Proficiency in logic
design, simulation
Excellent analytical and problem-solving skills. Quick learner-
able to learn and apply technical and complex topics.
Excellent communication skills and the uncanny ability in a
cooperative team environment are required.
Self-motivated, result-oriented, can take ownership and follow-
through on tasks.
Position Requirements:
Essential Qualifications:
Master or PHD degree
Major in Micro-Electronics, Electronic Engineering, Computer
Science, Information Technology, Mathematics, Physical or
equivalent
Ability to work effectively alone or as well as in a team.
Essential that the individual demonstrates strong communication,
verbal and written
Requires good communication skills in English. Desirable
Qualifications:
Solid Hardware, Software and Embedded System knowledge
Knowing ARM-based SOC design architecture, Knowing AMBA bus. Be
familiar with CPU/DSP architecture.
Knowledge of USB2.0/3.0, PCI/PCIE, HDMI, Display Port
7. Design Engineer – digital frontend (Location: SH) - campus
recruitment
(Req #: 7068, 7069, 7070)
Position Description:
In charge of IP and SOC logic design, verification and
Implementation.
Daily duties include: Digital IC micro-architecture, RTL coding,
Logic Synthesis, Function Verification, DFT, and Static Timing
Analysis.
HDL language Knowledge, like verilog or vhdl is necessary.
C/C++/perl/tcl/csh, UNIX, Linux experience are plus.
Excellent analytical and problem-solving skills. Quick learner-
able to learn and apply technical and complex topics.
Excellent communication skills and the uncanny ability in a
cooperative team environment are required.
Self-motivated, result-oriented, can take ownership and follow-
through on tasks.
Position Requirements:
Essential Qualifications:
Master degree or above
Major in Micro-electronics, Electronic Engineering, Computer
Science, Information Technology or equivalent
Ability to work effectively alone or as well as in a team.
Essential that the individual demonstrates strong communication,
verbal and written
Requires good communication skills in English. Desirable
Qualifications:
Good at any following skill sets: ASIC design, FPGA design,
Computer architecture, SOC design based on ARM/MIPS.
Experience of USB2.0/3.0, PCIE,HDMI, Display Port
☆─────────────────────────────────────☆
eematlab (皮皮朱) 于 (Thu Nov 1 22:21:54 2012) 提到:
放公司邮箱不好
推荐你认识的人较好
为了推荐费在论坛发贴的行为不赞成
【 在 masking (马斯金) 的大作中提到: 】
: 代友发文，勿站内。
: 英文简历发送至 xiny@cadence.com 注明职位。
: JD：
: ...................
☆─────────────────────────────────────☆
masking (马斯金) 于 (Thu Nov 1 22:47:57 2012) 提到:
都是你情我愿的事情 有什么不好
【 在 eematlab (皮皮朱) 的大作中提到: 】
: 放公司邮箱不好
: 推荐你认识的人较好
: 为了推荐费在论坛发贴的行为不赞成
☆─────────────────────────────────────☆
eematlab (皮皮朱) 于 (Thu Nov 1 22:54:20 2012) 提到:
推荐的目的是希望你推荐你所认识的人，你能够透露他一些真实的情况，因为面试时间太短，很难去真实的全面的了解一个人。
以上只是我个人观点，是从招人角度考虑问题的
你说的也没错，举手之劳，赚点公司的外快也没错
【 在 masking (马斯金) 的大作中提到: 】
: 都是你情我愿的事情 有什么不好
☆─────────────────────────────────────☆
eematlab (皮皮朱) 于 (Thu Nov 1 23:13:17 2012) 提到:
1. 猎头做的不是forward一份简历这么简单
2. 认识和有私人关系并不等价，看你怎么定义“私人关系了”
3. 公司不禁止有私人关系，小公司的话，可能所有人私下都玩的很好。
4. “推荐”，准确地说是“推”你认识不错的人，和forward陌生人的简历还是有点区别的
5. 如果只是收集简历，其实HR们可以有更廉价地方式（肯定比付推荐费便宜地多）
当然如果你收到简历，然后对他们先进行电话筛选，那么我承认我说错了
【 在 buf (戒烟这事，太难了。) 的大作中提到: 】
: 推荐的目的是让你给予这个领域的同仁，而省去找猎头的麻烦。
: 至于是不是一定要了解这个人不是必须的。否则那还要面试作什么？
: 照你那个推理，恐怕一个公司内部都是有私人关系的了。
☆─────────────────────────────────────☆
cassiopeia (thinker) 于 (Fri Nov 2 13:16:29 2012) 提到:
错别字多了些，HR MM们也不先检查一下就copy。对Emulation AE职位感兴趣，可惜在SH，去不了。
【 在 masking 的大作中提到: 】
: 代友发文，勿站内。
: 英文简历发送至 xiny@cadence.com 注明职位。
: JD：
: ...................
masking (马斯金) 于 (Thu Nov 1 19:46:09 2012) 提到:
代友发文，勿站内。
英文简历发送至 xiny@cadence.com 注明职位。
JD：
Shanghai R&D Vacancies (Nov. 2012) RD, PE, PV & Internship
R&D
1. Senior Software Engineer for Encounter Hier Solution Team (Req#:
6638)
Position Description
The candidate will be a member of the Encounter Hier Solution
team in Shanghai, to work on the development and maintenance of
Hier Solution project.
The responsibilities include development of new features and
products, and support other teams in Encounter product lines.
The candidate must be comfortable working with existing code as
well as developing new functionality to address new requirements,
and be working closely with local/remote team members, and be also
strong technical support to team.
Position Requirements
Candidate must be an expert in software engineering methods and
committed to high quality of development work.
The individual must be team-oriented, possess good communication
skills, self-motivated, able to work independently and working with
a team from multiple remote sites.
Candidate must be able to develop detailed technical
specification as well as the ability to scope efforts required.
The candidate must be also smart to capture new EDA technologies,
and switch among different areas successfully.
Advanced developing and debugging software in UNIX & LINUX
environments, familiar with gnu c/c++, gdb etc..
Strong problem-solving, architecture, algorithmic.
Familiar with interpreted language such as TCL is a plus.
Knowledge of Timing analysis is a plus。
2. Senior Software Engineer for EDI IPO (Req#: 7035, 7036, 7037,
7038, 7039)
Position Description
Working on EDI IPO function on CCR fixing, memory and performance
profiling as well as new enhancements.
Position Requirements
MS/PHD from computer science, EE, math or related
The candidate must be also smart to capture new EDA technologies,
and switch among different areas successfully.
Strong problem-solving, architecture, algorithmic.
Familiar with interpreted language such as TCL is a plus.
3. Senior Product Engineer (Req#: 6934)
Position Description
As a Product Engineer for Cadence’s Encounter Test product group,
you’ll have the opportunity to apply your academic background and
project based experience to the challenge of enabling our customers
to utilize our key test technologies such as Design-For-Test (DFT)
structures, Automatic-Test-Pattern-Generation (ATPG), and
Diagnostics. Your challenge will be to make our customers
successful in meeting their test cost and quality metrics, using
the leading-edge tools in the Encounter Test product family.
Through your training period, you’ll be mentored by a senior team
member with years of industry experience in test, and you’ll have
the opportunity to differentiate yourself by bringing your unique
skills to the challenge. Our customers consist of many of the
leading chip design teams in the industry, and they’ll count on you
for your expertise in enabling them to test their critical products
in an effective manner.
If you’re looking for a challenging work environment, as part of a
fast paced, close-knit, and technologically advanced team, then we’
re looking for you.
Other responsibilities of the product engineering position
include:
Interfacing and working with directly R&D
Interfacing directly with field application engineers and
customers
Supporting and debugging customer test design methodologies using
our products
Optimizing product documentation, application notes, videos,
training and demos to facilitate product adoption
Enhancing product usability by both advocating for product
changes, and improving product support collateral
Position Requirements
MSEE/MSCE required
2-4 years of related industry experience
Excellent communication skills (written and verbal)
Strong programming and scripting skills
Strong group presentation skills
Familiarity with Test fundamentals (DFT, ATPG and Diagnostics
concepts)
Coursework and/or project-based experience dealing with the
digital design process
Experience with Cadence or other EDA/test tools a plus
Good command of the English language, both written and spoken –
Required
4. Software Engineer for Memory Modeling (Req#: 6958)
Position Description
Responsible for designing and developing models of system level
memories like DDR SDRAM, NAND Flash, EEPROM and eMMC for use on
hardware based verification products.
In addition modifying, updating, maintaining and productizing
existing system level memory model products.
Perform as individual contributor involving RTL design,
verification, productizing and documentation.
Work on moderately complex problems related to emulation,
simulation or verification issues.
Position Requirements
The position requires BSEE, or equivalent, with a minimum of 2
yrs of industry experience in designing hardware systems.
Must have excellent communication skills, both written and
verbal.
RTL design knowledge using Verilog is required along with
experience in using RTL verification tools and flows.
In addition Verification using Cadence simulation products is
desired as is Verification experience using emulation products.
Experience with scripting languages like Perl, TCL C-shell is
strongly recommended.
5. Senior Software Engineer for HDL Compiler (Req#: 6933)
Position Description
Responsible for designing, developing, troubleshooting and
debugging software programs on Linux/Unix platforms.
Develops electronic design automation (EDA) software tools
involving RTL synthesis, hardware emulation and design
verification.
Works on complex problems where analysis of situations or data
requires an in-depth evaluation of various factors.
Exercises judgment within broadly defined practices and policies
in selecting methods, techniques, and evaluation criteria for
obtaining results.
Utilizes and integrates various EDA tools for synthesis,
simulation, verification acceleration, and formal verification.
Works together with an R&D group in Silicon Valley of the United
States.
Position Requirements
MS in EE/CS required. Pd.D. in EE/CS preferred.
Proficiency in English reading and writing.
Proficiency in C++/C programming on Linux platform.
Knowledge in digital IC design.
Knowledge in Verilog, VHDL, or SystemVerilog.
Knowledge in logic synthesis, simulation, formal verification, or
emulation preferred.
6. Senior Software Engineer for CTS
Position Description
The primary responsibility is designing, developing,
troubleshooting and debugging software programs on Unix/Linux
platforms. Will be involved in CTS development for Encounter.
Position Requirements
MS in EE/CS with 2+ years or PhD in EE/CS
Strong physical design (EDA) background (Digital IC)
Excellent programming skills (C/C++, script)
Good written and spoken English
Good communication skills and be able to work both independently
and in a team.
R&D engineer to do the clock tree/mesh synthesis related works
(software development, design flow improvement)
PE
1. Product Engineer for GUI and usability (Req#: 6846)
Position Description
Work on Encounter Digital Implementation system Graphic User
Interface features.
Understand and define customer requirements. Work with RD and
global cross-function-team to ensure the development can fulfill
customer requirements and methodology.
Position Requirements
Master degree and majored in EE/CS/EDA
Familiar with IC physical design flow
with GUI and usability sense for user interaction
Fluent English in both oral and written
2. Principal Product Engineer for Cadence PDK (Req#: 7032)
Position Description:
Work in Cadence Foundry Access Team based in Shanghai. Major
responsibilities include:
To provide key technical support in Cadence PDK implementation
for our foundry partners in Shanghai;
Support customers in Cadence PDK application thru whole Cadence
Custom IC design flow
In charge of Custom IC reference flow development.
Position Requirements:
A bachelor's degree is essential and 9+ years experience, or
master's degree with 7+ years experiences in PDK development or
Custom IC design flow applications.
Strong scripting capability, including Skill/Shell/Perl.
Expertise in Custom IC data format, including CDF, PCell, CDL,
GDSII, av_extracted view, Virtuoso techfile, etc.
Familiar with Cadence CIC tools, including IC5141/IC61 platform,
Spectre, AMS designer, Assura, QRC, etc.
Ability to understand and articulate technical issues, (and
knowledge of) design products and their applications.
Good communication in English and Chinese, team spirit, self-
confidence and self-motivation.
Internship
1. PV Intern for GPS (Global Physical Synthesis) (Req#: 7033)
Position description
This intern will work in ICD (P&R) Product Validation team. The
responsibilities include:
Assist in Cadence GPS product and engine's development and
validation
Validate comprehensive GPS test cases for Encounter Digital
Implementation System
Develop and maintain system and infrastructure for high
productivity and efficiency with various scripting and system
development techniques
Position Requirements
MS or excellent undergraduate, Strong perl programming
experience.
IC design knowledge is necessary, statistic timing analysis
knowledge is a strong plus
Unix System knowledge, vi/TCL/TK/CSH will be plus.
Good communication in English and Chinese, good confidence and
good self-motivation.
2. PV Interns - System and Regression(Req#: 7084)
Position description
Need 4 days/week or full time working with PV regression team for
system enhancement
Help PV team on scripts development.
Position Requirements
MS or excellent undergraduate, Strong perl programming
experience.
IC design knowledge is necessary, such as statistic timing
analysis
Unix System knowledge, vi/TCL/TK/CSH will be plus.
Good communication in English and Chinese, good confidence and
good self-motivation.
3. PV Intern for STA (Static Timing Analysis)
Position description
This intern will work in Encounter Common Timing Engine Product
Validation team. The responsibilities include:
Assist in Cadence STA product and engine's developement and
validation
validate comprehensive STA testcases for Encounter Digital
Impelementation System and Encoutner Tming System
Develope and maintain system and infrastructure for high
productivity and efficiency with various scripting and system
developement techniques
Position Requirements
MS or excellent undergraduate
Digital IC design knowledge is necessary, statistic timing
analysis knowledge is a strong plus
Unix System knowledge, vi/TCL/TK/CSH/Perl will be plus.
Good communication in English and Chinese, good confidence and
self-motivation.
Commitment to work as intern for at least 6 months
Beijing RD & PE Vacancies (Nov.2012)
R&D
1. Member of consulting staff for Cadence Virtuoso Environment
(Location:BJ) ( Req#: 6332)
Position Description
The Cadence Virtuoso platform powers all of the latest design
innovations in consumer, mobile and enterprise electronics
worldwide. We are looking for an exceptional senior software
engineer to join our team and contribute to the continued growth
and success of the company’s flagship product. In this high-impact
career opportunity, you will lead design and development of
cutting-edge features of some of our most exciting new products,
with an emphasis on circuit simulator integration in the Virtuoso
ADE/ADE XL environment. You will contribute both individually and
as a technical lead, working with a cross-functional team in
Beijing and San Jose to ensure that our software is developed,
tested, and documented with high quality.
Position Requirements
Exceptional C++ programming and familiarity with Linux/Unix
development.
Experience with GUI frameworks, such as Qt.
Strong scripting language skills in one or more of: Python, Perl,
Lisp, Tcl.
Proficiency with build and version-control systems.
Excellent written and oral English communication skills.
Coursework or work experience in electronic circuit design.
Exposure to the Cadence Virtuoso environment or other electronic
design platforms.
B.S. in engineering, computer science or related field. Graduate
degree preferred.
2. Senior Member of Technical Staff, Simulation Integration
(Location:BJ) ( Req#: 6937)
Position Description
World’s leading design companies rely on Cadence technologies to
deliver the latest design innovations in consumer, mobile and
enterprise electronics. We are looking for exceptional software
engineers to join our team and contribute to the continued growth
and success of the company’s flagship products, such as Virtuoso
Spectre and Virtuoso ADE. In this high-impact career opportunity,
you will develop cutting-edge features of some of our most exciting
new products, with an emphasis of scripting language development
and GUI integration. You will work with a cross-functional team in
Beijing and San Jose to ensure that our software is developed,
tested, and documented with high quality.
Position Requirements
Strong C++ programming and familiarity with development under
Linux/Unix environment.
Proficiency with linux/unix tools.
Skills in one or more of script such as Python, Perl.
Familiar with build and version-control systems.
Good English communication skill both verbally and writing.
Good problem solving skill and team work spirit.
Preferred Skills
Experience in the use of parser generators, such as Antlr or
Yacc/Lex
Exposure to circuit simulators, such as SPICE, HSPICE and
Spectre.
Coursework or work experience in analog or mixed-signal circuit
design
Education
EE, computer science or related field.
3. Member of Technical Staff-Virtuoso ADE XL software
developer(Location:BJ) ( Req#: 5918)
Position Description
Custom digital and analog circuit designers must generate and
interpret large amounts of complex simulation data. Virtuoso ADE XL
accelerates design by enabling setup reuse, parallelizing compute-
intensive simulation, and through extensive post-processing and
visualization capabilities. We are seeking a talented software
developer to improve simulation throughput and data visualization.
Position Requirements
Demonstrated proficiency in C++ and general software development
skills
BS in Computer Science or Computer Engineering required.
XML, SQL, GUI (Qt specifically), and distributed processing
experience a plus.
Experience with Cadence Virtuoso or analog circuit design is a
plus.
4. Member of Consulting Staff (Location:BJ) ( Req#:6158)
Position Description
The position is for analog circuit simulation engineer
responsible for designing, implementing and maintaining device
compact models in SPICE-like circuit simulation software for use
with analog, RF and mixed signal circuit simulators. The engineer
will be responsible for leading multiple development efforts
through the development process, including writing specifications
based on marketing and product requirements, designing and
implementing product improvements and fixes, and working with a
cross-functional team to ensure the software is tested, integrated
and documented. The engineer must be proficient in C/C++ Unix
development, and have a thorough knowledge of device physics,
device compact models. The engineer must have a proven ability to
learn from and work with an engineering and cross-functional team
to deliver innovative products in a production environment.
Position Requirements
Well devices physics, device compact models;
Familiar with matrix solver & mathematic calculation;
Familiar with Spice, Spectre format & usage;
Skilled in C++ programming, familiar with development under
Linux/Unix environment;
Be familiar with Analog-signal design is a plus;
Good English communication skill both verbally and writing;
Good problem solving skill and team work spirit;
5. Senior member of technical staff - Characterization RD
(Location: BJ) ( Req#:5879)
Position Description
The positions are for a developer who will be responsible for
designing, implementing, and maintaining library characterization
and validation software for use with standard cells, memory and
macro blocks, and IO cells.
Position Requirements:
The candidates should have two or more years of experiences in
developing EDA software.
Must be proficient in C, C++, TCL, and development in Linux/Unix.
Knowledge on semiconductor device is strong plus.
Experience with SPICE or SPICE-like circuit simulation is
important.
Knowledge of Verilog and VHDL is also highly desirable.
Have a good understanding of library characterization, IP design,
static timing analysis, power analysis, and signal integrity
analysis flows.
Minimum Education Required / Minimum Experience Required : MS,
EE, CS, Math or Physics 2
Preferred Education / Preferred Experience: Ph.D. , EE, CS, Math
or Physics 3-5
6. Senior member of technique staff for Verilog-A simulator
development (Location: BJ) ( Req#:7098)
Position Description:
Develop, enhance and maintain Verilog-A simulator.
Position Requirements:
Familiar with Spice, Verilog-A, Verilog-AMS language
Skilled in C++ programming, familiar with development under
Linux/Unix environment.
Analog circuit or digital simulator development experiences.
Well understanding on circuit simulation technology, including
MNA, dc, tran method.
Good mathematic background & knowledge.
Be familiar with Analog Mixed-signal design is a plus
EE or CS Master degree with at least 2 years related working
experience or above
PE
1. Senior Product Engineer – Characterization (Location: BJ)
(Req#:5546)
Position Description
The Altos Product Engineer (PE) works with key customers to
understand their library characterization challenges, maps
Customer needs into product requirements, and collaborate with
the R&D and PV organization to ensure that the product
Implementation addresses the customer’s real needs.
The Altos PE plays a pivotal role in defining and deploying
Cadence’s library characterization products and solutions at key
customers that enable them to do characterization at a very high
performance & efficiency.
This position requires problem discovery and analysis at customer
site, assessment of possible solutions, collaborating with RD and
customer to develop and test the solution, and managing it’s
deployment at the customer site.
Position Requirements:
The candidate should possess minimum a Bachelors technical degree
and 3-5 years of industry experience
Minimum 3 years hands-on, expertise on library characterization,
IP design, static timing analysis, power analysis, and signal
integrity analysis flows.
Hands on Design experience using Verilog, VHDL
Experience with SPICE or SPICE-like circuit simulation is strong
plus
Knowledge on semiconductor device is strong plus.
Knowledge on competitor characterization flow and tools is a plus
Highly technical & hands on engineer with an ability to partner
with key customers and provide expert support to field application
engineers.
The candidate must be able to drive R&D and Application engineers
and have passion to make customers successful.
She/he must be willing to travel worldwide in order to work
closely with customers in any part of the world.
Passionate about adopting and promoting new technologies and
making customers successful.
Successful in building and delivering training content on rolling
out new products/methodologies
Very good communication skills and a strong desire for working in
a global environment with customers Developers, marketing and
sales.
English fluency is a must, Korean speaking language is a plus
AE & Solution Engineer Vacancies (Nov. 2012)
1. Lead/Principle Application Engineer – ICD backend support
(Location: BJ/SH)
(Req #: 6835, 6836)
Position Description:
To provide key technical support in digital IC design
implementation, product demonstration, and sales presentations.
To demonstrate strong ability and to be hands-on in RTL-to-GDSII
design methodology, for challenging low power designs, for 200MHz
to several GHz big chips.
Have real design experience including conformal check, logic
synthesys, P&R, CTS, SSTA, MMMC to close timing, power and die
area.
Assist in technical evaluation, assessment and delivery of
concurrent ASIC/SoC designs. To play a leading role among other
team members, while receive little instruction on routine and
general assignments.
Position Requirements:
Bachelor's degree with 7+ years experience in IC design, majoring
in electronic engineering or computer science applications.
Mater degree and/or working experience in multi-nation IC design
house is preferred.
Ability to understand and articulate technical issues, (and
knowledge of) design products and their applications.
Requires working knowledge of one or more programming languages,
and effective communication and soft skills
3. Lead Application Engineer AMS (Location: SH) (Req #:6762)
Position Description:
Provide technical support for Cadence Custom IC front to back
design flow. Mainly focus on analog/RF/mixed-signal circuit
simulation products support.
Has thorough understanding of Cadence Virtuoso solution
marketplace and objectives, including key players, products and
trends.
Support sale to address customers' technical demand to propose
and deliver value position for maximizing business opportunities.
Conduct Cadence Virtuoso products demonstration, presentation,
workshop and benchmark to address the customer's technical
concerns.
Provide post-sales support such as products training, software
environment maintain, products usage guide to assure customer
satisfaction and nurture future sales potentials.
Ability to openly exchange and communicate technical information
with peers, group management, and customers.
Position Requirements:
Bachelor's degree majoring in electronic engineering or computer
science applications, with 5+ years experience in Analog and RF IC
design.
Mater degree and/or working experience in multi-nation IC design
house is preferred.
Strong verbal and written skills in English are required.
Have good communication skill and teamwork spirit.
4. Lead Application Engineer (Location: SH) (Req # 6765)
Position Description:
Work closely with the Sales team to identify and scope
opportunities for Cadence Emulation and Acceleration products.
Plan, execute and manage key technical evaluations and benchmark
with existing and potential customers.
Train, ramp-up and accompany customer project.
Conduct basic and advanced trainings, presentations and demos as
necessary.
Providing technical expertise to address clients’ queries, which
need expert involvement.
Aligned closely with corporate engineering and sales/marketing
team on customer requirement for product direction/improvement.
Position Requirements:
4~6 years experience in the following areas:
HW verification with knowledge of System Verilog/VHDL and HDL
simulators
FPGA prototyping project experience is a must
Experience with hardware emulator or accelerator is a big
advantage
Advanced Verification Methodology like OVM or VMM is a plus
Knowledge of UNIX and Linux is highly desired
Strong verbal and written communication skills in English
Strong teamwork skills with good human relationship
5. Technical Lead/ Lead Service Engineer of methodology group
(Location:
BJ/SH/SZ) (Req #:6734, 6735, 6736)
Position Description
This position requires excellent design experiences in the
digital implementation domain including Floorplan, P&R, STA,
Physical verification, DFM.
Must have a solid background in circuits, electronics & physics &
should be very willing to learn new stuff.
Responsible for large sized design implementation tasks &
architectural tasks, which requires ability to assess Customer's
Design environment, to understand his application needs & to build
new Design environment based on specifications & available Cadence
tool technology.
Ability to acquire a basic understanding of the (services)
business environment of Cadence within 1 month. Feeling responsible
for technical delivery as well as business development &
opportunity creation.
Behavioral competencies: Teamwork; Customer focus;
Accountability; Communication; Coaching & feedback; Leadership
Position Requirements:
MS degree with 10+/7+ years of applicable experience in
electrical engineering, microelectronics.
Essential that the individual demonstrates strong communication,
verbal and written, and project management skills.
Good verbal and written communication skill in English is needed.
Will have demonstrated hands-on experience and expertise with
Cadence logical and physical design tools (SoC Encounter,
Conformal, QRC, Vstorm, ETS/CNDC, and PVS) or equivalent tools,
flows and methodologies required to execute a physical design
project.
Will have demonstrated successful completion of 5+ physical chip
implementation projects through to tape (better to have 65nm or
hierarchical implementation experience) as an individual
contributor
Will have demonstrated successful completion of at least ten
physical design projects as a technical leader.
Able to work on-site at customer premises, travel up to 30%, and
put in long hours when required to meet customer deadline.
Experience in sign-off tools for STA, IR drop, power analysis, SI
analysis is a plus
Knowledge and experience in design for advanced process nodes
(40nm and below) is a plus.
6. Principle Solution Engineer – Verification
Position Description
The Incisive Solution Engineer works with key customers to
understand their design and verification challenges,
Collaborate with the R&D and PV organization to ensure that the
product implementation addresses the customers’ real needs.
The Solution Engineer plays a pivotal role in defining and
deploying Cadence’s Incisive Simulator products
and solutions at key customers to enables them to do functional
verification at a very high performance & efficiency.
This position requires problem discovery and analysis at customer
site, assessment of possible solutions,
Collaborating with R&D and customer to develop and test the
solution, and manage the deployment at the customer site.
The position also requires mentoring junior application engineers
on verification solutions and tool usage.
The position requires 100% presence in Asia Pacific area.
Position Requirements
The candidate should possess minimum a Bachelors technical degree
and 5-8 years of industry experience
- Minimum 5 years hands-on, expertise on simulation based design &
verification techniques.
- Hands on experience using HDL simulator is a must
- Knowledge on competitor verification flow and tools is a plus
- Hands on Verification experience using
SystemVerilog/e/SystemC/Vera
- Hands on Design experience using Verilog, VHDL, SystemC
- Hands-on experience optimizing RTL and Gate-level simulation to
improve performance is a plus
- Ability to partner with key customers and provide expert support
to field application engineers
The candidate must be able to drive R&D and Application engineers
and have passion to make customers successful
- Must be willing to travel worldwide in order to work closely with
customers in any part of the world
- Highly organized individual with demonstrated ability to handle
multi-task activities and projects
- Passionate about adopting and promoting new technologies and
making customers successful
- Building and delivering training content to roll out new solution
and methodologies
- Very good communication skills
- English fluency is a must, Chinese and/or Korean speaking
language is a plus
- Multi-years working experience with western companies (EMEA or
USA) is a plus
- Experience to lead projects and people will be strongly taken
into consideration
SoCR Vacancies – Nov 2012 (SH & BJ)
1. Lead Physical Design Engineer (Location: SH) (Req #: 6745)
Position Description:
Perform physical design implementation, including synthesis,
floor planning, power grid design, place and route, clock tree
synthesis, timing closure, power/signal integrity signoff, physical
verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure, and
physical design project management.
The candidate will have the opportunity to work on many varieties
of challenging designs, i.e. low power and high speed design. The
responsibility includes participating in or leading next generation
physical design, methodology and flow development.
Position Requirements:
BS degree with 10+ years of applicable experience, MS degree with
7+ years of applicable experience in electrical engineering,
microelectronics. Experienced with ASIC design flow, hierarchical
physical design strategies, and methodologies and understand deep
sub-micron technology issues.
Solid knowledge on LP Design, DFT, static timing analysis, EM/IR-
Drop/crosstalk analysis, formal verification, physical
verification, DFM.
Successful track records of taping out complex, 65/40/28 nm SOC
chips.
Automation and programming-minded, solid coding experience in
Makefile/Tcl/Tk/Perl.
Self-motivated, able to work independently or as a team player,
excellent verbal and written communication skills in English.
2. Lead Implementation design Services Engineer (Location: SH) (Req
#:6662)
Position Description:
The candidates should be senior in a way that they are not only
technical excellent but also mature & able to communicate with
customers, following team members. This engineer should have
excellent design experiences in the digital implementation domain
including Floor plan, P&R, STA, Physical verification, DFM. The
engineer must have a solid background in circuits, electronics &
physics & should be very willing to learn new stuff.
Position Requirements:
Ability to handle large sized design implementation tasks &
architectural tasks alone.
Ability to assess Customer's Design environment, to understand
his application needs & to build new Design environment based on
specifications & available Cadence tool technology.
Ability to acquire a basic understanding of the (services)
business environment of Cadence within 1 month.
Working on multi person projects of varying complexity, working
especially in a multi-site/multi-cultural project.
The latter requires good communication skills in English.
Feeling responsible for technical delivery as well as business
development & opportunity creation.
Behavioral competencies: Teamwork; Customer focus;
Accountability; Communication; Coaching & feedback; Employee
development; Leadership.
3. Principle Design Engineer – SoC Architecture & Algorithm
(Location: SH)
Position Description:
In charge of SoC Spec definition, chip or complex IP architecture
design. The engineer should be able to leading projects and
initiatives. Exercise judgment within generally defined practices
and policies.
Algorithm study, modeling and verification.
Specific duties include: - Be responsible for the design micro-
architecture, system and test platform development - Proficiency in
logic design, simulation - Proficiency in Verilog and its
simulation environment -At least six years experience on driving
complex IC development projects on wired/wireless telecom and high
speed interface, excellent communication skills and the uncanny
ability to both lead and contribute in a cooperative team
environment is required.
Position Requirements:
Have BS degree with 12+ years of applicable experience, MS degree
with 10+ years of applicable experience or PhD degree with 6+ years
of applicable experience in architecture and system. Candidate must
have experience on mass product and hands on hardware verification
Strong knowledge with DSP and mixed signal design in Digital
communication, DTV or Multimedia.
Must have strong Mathematics skill. Knowledge of Matlab, or
C/C++, or System C, SystemVerilog or Verilog is necessary.
Experience of DSP based Architecture design. Good Knowledge of
CPU, DSP and GPU.
Good knowledge on wired high-speed interface standard
Ability to work effectively alone or as well as in a team.
Essential that the individual demonstrates strong communication,
verbal and written
Requires good communication skills in English.
4. Staff/Principal SerDes Analog IC Design Engineer (Location: SH)
(Req #:6662)
Position Description:
Responsible for the design and development of SerDes analog/mixed
signal IC circuit blocks from initial concept and specification
through final verification and conformance to customer
requirements.
Candidate’s background should demonstrate good problem solving
skills, excellent analog aptitude, good communication skills, and
ability to work cooperatively in a team environment.
Must have demonstrated experience in SerDes transceiver designs
including some of the following circuit blocks: System level
modeling by matlab, C, or VerilogA; Driver; Receiver; Serializer;
Deserializer; Phase Interpolator; Low jitter PLL; High Speed Clock
Distribution; Bias and Bandgap; Voltage Regulators.
Have working knowledge of a set of common SerDes standards and
their electrical requirements, and a thorough understanding of
jitter.
Requires proficiency in using CAD tools for circuit simulation,
layout, and physical verification (Cadence tool experience, lab
test experience, and experience at 65nm and below technologies are
a plus).
Job Requirements:
BSEE [MSEE/Ph.D EE preferred]
Minimum 8 years experience in CMOS SerDes IC design
5. Design Engineer – Analog circuit (Location: SH) - campus
recruitment
(Req #: 7086, 7087)
Position Description:
In charge of analog and mixed-signal circuit design.
Hands-on experience conducting design analysis and recommending
appropriate solutions
Architecture study, modeling and verification.
Specific duties include: - Analog circuit simulation, layout
guidance, test chip measurement and debug
Excellent analytical and problem-solving skills. Quick learner-
able to learn and apply technical and complex topics.
Excellent communication skills and the uncanny ability in a
cooperative team environment are required.
Self-motivated, result-oriented, can take ownership and follow-
through on tasks.
Position Requirements:
Essential Qualifications:
Master or PHD degree, major in Micro-Electronics, Electronic
Engineering or equivalent
Ability to work effectively alone or as well as in a team.
Essential that the individual demonstrates strong communication,
verbal and written
Requires good communication skills in English. Desirable
Qualifications:
Knowledge of one of key Analog IC design areas and their
architectures/applications: Data Converters; PLL's; Oscillators;
Low Noise Design; RF IC building blocks
Solid understanding of IC design technology and
process/methodology in IC design solutions
Familiar with Cadence analog and mixed-signal EDA tools is a plus
6. Design Engineer – Algorithm & Architecture (Location: SH) -
campus recruitment
(Req #: 7071)
Position Description:
In charge of SoC Spec definition, whole chip or complex IP
architecture design.
Algorithm study, modeling and verification.
Specific duties include: - Owning the IC micro-architecture,
package and test platform development - Proficiency in logic
design, simulation
Excellent analytical and problem-solving skills. Quick learner-
able to learn and apply technical and complex topics.
Excellent communication skills and the uncanny ability in a
cooperative team environment are required.
Self-motivated, result-oriented, can take ownership and follow-
through on tasks.
Position Requirements:
Essential Qualifications:
Master or PHD degree
Major in Micro-Electronics, Electronic Engineering, Computer
Science, Information Technology, Mathematics, Physical or
equivalent
Ability to work effectively alone or as well as in a team.
Essential that the individual demonstrates strong communication,
verbal and written
Requires good communication skills in English. Desirable
Qualifications:
Solid Hardware, Software and Embedded System knowledge
Knowing ARM-based SOC design architecture, Knowing AMBA bus. Be
familiar with CPU/DSP architecture.
Knowledge of USB2.0/3.0, PCI/PCIE, HDMI, Display Port
7. Design Engineer – digital frontend (Location: SH) - campus
recruitment
(Req #: 7068, 7069, 7070)
Position Description:
In charge of IP and SOC logic design, verification and
Implementation.
Daily duties include: Digital IC micro-architecture, RTL coding,
Logic Synthesis, Function Verification, DFT, and Static Timing
Analysis.
HDL language Knowledge, like verilog or vhdl is necessary.
C/C++/perl/tcl/csh, UNIX, Linux experience are plus.
Excellent analytical and problem-solving skills. Quick learner-
able to learn and apply technical and complex topics.
Excellent communication skills and the uncanny ability in a
cooperative team environment are required.
Self-motivated, result-oriented, can take ownership and follow-
through on tasks.
Position Requirements:
Essential Qualifications:
Master degree or above
Major in Micro-electronics, Electronic Engineering, Computer
Science, Information Technology or equivalent
Ability to work effectively alone or as well as in a team.
Essential that the individual demonstrates strong communication,
verbal and written
Requires good communication skills in English. Desirable
Qualifications:
Good at any following skill sets: ASIC design, FPGA design,
Computer architecture, SOC design based on ARM/MIPS.
Experience of USB2.0/3.0, PCIE,HDMI, Display Port
☆─────────────────────────────────────☆
eematlab (皮皮朱) 于 (Thu Nov 1 22:21:54 2012) 提到:
放公司邮箱不好
推荐你认识的人较好
为了推荐费在论坛发贴的行为不赞成
【 在 masking (马斯金) 的大作中提到: 】
: 代友发文，勿站内。
: 英文简历发送至 xiny@cadence.com 注明职位。
: JD：
: ...................
☆─────────────────────────────────────☆
masking (马斯金) 于 (Thu Nov 1 22:47:57 2012) 提到:
都是你情我愿的事情 有什么不好
【 在 eematlab (皮皮朱) 的大作中提到: 】
: 放公司邮箱不好
: 推荐你认识的人较好
: 为了推荐费在论坛发贴的行为不赞成
☆─────────────────────────────────────☆
eematlab (皮皮朱) 于 (Thu Nov 1 22:54:20 2012) 提到:
推荐的目的是希望你推荐你所认识的人，你能够透露他一些真实的情况，因为面试时间太短，很难去真实的全面的了解一个人。
以上只是我个人观点，是从招人角度考虑问题的
你说的也没错，举手之劳，赚点公司的外快也没错
【 在 masking (马斯金) 的大作中提到: 】
: 都是你情我愿的事情 有什么不好
☆─────────────────────────────────────☆
eematlab (皮皮朱) 于 (Thu Nov 1 23:13:17 2012) 提到:
1. 猎头做的不是forward一份简历这么简单
2. 认识和有私人关系并不等价，看你怎么定义“私人关系了”
3. 公司不禁止有私人关系，小公司的话，可能所有人私下都玩的很好。
4. “推荐”，准确地说是“推”你认识不错的人，和forward陌生人的简历还是有点区别的
5. 如果只是收集简历，其实HR们可以有更廉价地方式（肯定比付推荐费便宜地多）
当然如果你收到简历，然后对他们先进行电话筛选，那么我承认我说错了
【 在 buf (戒烟这事，太难了。) 的大作中提到: 】
: 推荐的目的是让你给予这个领域的同仁，而省去找猎头的麻烦。
: 至于是不是一定要了解这个人不是必须的。否则那还要面试作什么？
: 照你那个推理，恐怕一个公司内部都是有私人关系的了。
☆─────────────────────────────────────☆
cassiopeia (thinker) 于 (Fri Nov 2 13:16:29 2012) 提到:
错别字多了些，HR MM们也不先检查一下就copy。对Emulation AE职位感兴趣，可惜在SH，去不了。
【 在 masking 的大作中提到: 】
: 代友发文，勿站内。
: 英文简历发送至 xiny@cadence.com 注明职位。
: JD：
: ...................