Re: 问个后端问题
时间：12-12
整理：3721RD
点击：
what you mentioned is the setup time margin and hold time margin?
if your chip P/R is done, setup time margin should be PLL cycle to cycle jitter.
hold time margin is more cirtical than setup margin, it always decided by foundry process. you can check the hold time margin setting according to foundry standard design flow.
if are doing STA on some early development stages, setup/hold time margin should reserve more space for future clock skew / routing / noise... too many factors are involved in the margin setting.
if your chip P/R is done, setup time margin should be PLL cycle to cycle jitter.
hold time margin is more cirtical than setup margin, it always decided by foundry process. you can check the hold time margin setting according to foundry standard design flow.
if are doing STA on some early development stages, setup/hold time margin should reserve more space for future clock skew / routing / noise... too many factors are involved in the margin setting.
10纳米。。。。你是问纳秒吧。。。。
你的问题很不清楚，是问violation还是margin？
400M的话，10ns都两个半周期了吧，做multi-cycle-path都可以了