ESPV-C是哪个公司的工具

显然是S公司的
ESP-CV™
        Functional Verification for Full Custom Designs  
ESP-CV verifies that two different design representations are functionally equivalent. These designs may be described as Verilog behavioral models, RTL, UDP’s, gates, transistors, or SPICE netlist views.
Benefits
Higher Quality
ESP-CV provides fast and complete coverage, enabling you to quickly find bugs and have the confidence that the reference model is functionally identical to the transistor model.
Increased Productivity
With ESP-CV, you no longer have to derive directed and random tests or have a long delay in releasing models while you complete your verification suite.
Easy to Use
ESP-CV directly verifies the SPICE netlist, eliminating the need to manually extract transistor network into a gate-level representation.

请教一个问题，ESP-CV是基于什么原理去保证一致性的？