请教ic compiler里面tie hi、tie LOW 线的链接

warning： Cell contains tie connections which are not connected       to rea
l PG.
icc_shell> derive_pg_connection -power_net VDD -power_pin VDD -ground_net VS
S -ground_pin VSS -tie
begin derive_pg_connection...
-- reconnected total 0 tie highs and 0 tie lows
1
icc_shell> check_mv_design -power_nets
。。。。。。。。。。
Warning: Total 89 logical library cell(s) used in the design do not have pow
er/ground pins. (MV-597)
Power/Ground Connection Summary:
P/G net name                P/G pin count
--------------------------------------------------------------------
Unconnected power pins:           11268
Unconnected ground pins:          11268
--------------------------------------------------------------------
Warning: Power connection/checking is skipped for 22536 power pins because t
he required power pin information cannot be found in logical libraries. (MV-
510)
No Errors/Warnings Found.
----------------------------------------------------------------------------
----
       Supply Operating Voltage Checks
----------------------------------------------------------------------------
----
No Errors/Warnings Found.
Please review report above for warnings and errors.
1
foundry提供的library 就是这个了，好像也没有其他D的“ logical libraries    wi
th power pins.”
这个应该如何处理？谢谢

不是每个牛奶都叫特仑苏
不是每个power pin都叫VDD
先check power pin name，再check哪些pin要连tie，再check库~

-tie不是这个意思……
先man一下这个命令的用法再说吧

这个用check_mv_design -verbose -power_nets看过了。确实是VDD，Vss