看了isscc2008的data converter部分
时间：12-11
整理：3721RD
点击：
感觉真是太牛了
12.1 An 820μW 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOS
12.2 Highly Interleaved 5b 250MS/s ADC with Redundant Channels in 65nm CMOS
12.3 A 150MS/s 133μW 7b ADC in 90nm Digital CMOS Using a Comparator-Based
12.4 A 1.9μW 4.4fJ/conversion-step 10b 1MS/s Charge-Redistribution ADC
12.5 A 9.4-ENOB 1V 3.8μW 100kS/s SAR ADC with Time-Domain Comparator
12.6 A 14b 100MS/s Pipelined ADC with a Merged Active S/H and First MDAC
12.7 A 1.2V 4.5mW 10b 100MS/s Pipelined ADC in 65nm CMOS
12.8 A 2.2mW 5b 1.75GS/s Folding Flash ADC in 90nm Digital CMOS
12.1 An 820μW 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOS
12.2 Highly Interleaved 5b 250MS/s ADC with Redundant Channels in 65nm CMOS
12.3 A 150MS/s 133μW 7b ADC in 90nm Digital CMOS Using a Comparator-Based
12.4 A 1.9μW 4.4fJ/conversion-step 10b 1MS/s Charge-Redistribution ADC
12.5 A 9.4-ENOB 1V 3.8μW 100kS/s SAR ADC with Time-Domain Comparator
12.6 A 14b 100MS/s Pipelined ADC with a Merged Active S/H and First MDAC
12.7 A 1.2V 4.5mW 10b 100MS/s Pipelined ADC in 65nm CMOS
12.8 A 2.2mW 5b 1.75GS/s Folding Flash ADC in 90nm Digital CMOS
贴下vlsi2008的adc部分，前几天刚完的
A 9.4-bit, 50-MS/s, 1.44-mW Pipelined ADC Using Dynamic Residue Amplification
A Fully-Differential Zero-Crossing-Based 1.2V 10b 26MS/s Pipelined ADC in 65nm CMOS, 161fJ
A 12b 50MS/s 10.2mA 0.18μm CMOS Nyquist ADC with a Fully Differential Class-AB Switched OP-AMP
A Process-Scalable Low-Power Charge-Domain 13-bit Pipeline ADC,140mW, 250Ms/s，0.28pJ,这一篇太牛了，号称mit十几年的研究成果，第一次在ieee发表
感觉你功耗写的不太对，我刚看到以为是自己错了
后来看了看paper，功耗没有你写的这么低...
我就看到session的abstract，同求。。。。。。