求助 在线等!
第一个问题:
我在做PCB元件封装时,REF DES 在丝印层的线宽是0,看到可以在出片时定义未定义线宽解决,但我想在画图时就预先设好,请问怎么设置?
第二个问题:
在做电阻原理图封装时,做了个PART TABLE,在做校验时报错.下面是信息,请帮忙分析:
schlib :: For pack_type 'DEFAULT' : Packager-XL Reported error.
pxl.log follows...
______ start pxl.log ______
Cadence Design Systems, Inc.
Packager-XL 15.20-p001 WIN32 28-May-2004 12:00:00 IST
(C) Copyright 1994, Cadence Design Systems, Inc.
Run on Fri Jul 06 10:35:30 2007
**********************************************
* Processing project file and command line *
**********************************************
ANNOTATE 'BODY' 'PIN'
COMP_DEF_PROP 'ALT_SYMBOLS' 'JEDEC_TYPE' 'NC_PINS' 'MERGE_NC_PINS'
'POWER_GROUP' 'POWER_PINS' 'MERGE_POWER_PINS' 'PINCOUNT'
COMP_INST_PROP 'GROUP' 'ROOM' 'REUSE_INSTANCE' 'REUSE_ID' 'REUSE_NAME'
'SIGNAL_MODEL' 'DEFAULT_SIGNAL_MODEL'
'VOLT_TEMP_SIGNAL_MODEL'
SUPPRESS_GLOBAL_SHORT_CHECK OFF
DEBUG 0
DESIGN_NAME xmpllib.xmpl_schlib:cfg_package
DEFAULT_PHYS_DES_PREFIX U
FEEDBACK 'OFF'
MAX_ERRORS 999
NET_NAME_CHARS @ - ! # % & ( ) * . / : ? [ ] ^ _ ` +
= > 0 1 2 3 4 5 6 7 8 9
NET_NAME_LENGTH 31
NUM_OLD_VERSIONS 3
OPTIMIZE OFF
REUSE_REFDES ON
OPF_OPTIMIZATION OFF
HARD_LOC_SEC OFF
FORCE_PTF_ENTRY OFF
REGENERATE_PHYSICAL_NET_NAME OFF
SCH_POWER_GROUP_WINS_OVER_PPT OFF
NULL_OPT_VALID OFF
USE_VECTOR_NOTATION ON
FILTER_ECS_FROM_XNET ON
OUTPUT 'ON'
PACKAGE_PROP 'GROUP' 'ROOM'
PART_TYPE_LENGTH 31
PPT E:/cadwork/low_doctor
REF_DES_LENGTH 31
REPACKAGE OFF
ELECTRICAL_CONSTRAINTS OFF
OVERWRITE_CONSTRAINTS OFF
RUN_DIR ./xmpllib/xmpl_schlib/packaged/
STRICT_PACKAGE_PROP 'REUSE_INSTANCE'
USE_LIBRARY_PPT ON
USE_STATE ON
WARNINGS ON
LIBRARY 'schlib' 'xmpllib' 'standard'
VIEW_PTF part_table
VIEW_PACKAGER packaged
VIEW_CONSTRAINTS constraints
DESIGN_LIBRARY xmpllib
DESIGN_NAME xmpl_schlib
VIEW_CONFIG_PHYSICAL cfg_package
SD_SUFFIX_SEPARATOR _
**************************************************************
* End processing project file and command line (00:00:00) *
**************************************************************
Creating Configuration "cfg_package" for Design "xmpl_schlib"
Loading d:\Cadence\SPB_15.2\share\cdssetup\cdsprop.tmf.
Loading d:\Cadence\SPB_15.2\share\cdssetup\cdsprop.paf.
*********************************
* Loading the design database *
*********************************
Loading e:/cadwork/schlib/resistor/part_table/part.ptf.
*************************
* Loading State Files *
*************************
State file pxl.state not loaded because not found.
*****************************************
* End loading State Files (00:00:00) *
*****************************************
****************************************
* Starting to assign physical parts. *
****************************************
#1 ERROR(1053): Cannot find a ppt part that matches the instance properties.
Ppt Name: RESISTOR
Schematic instance: @XMPLLIB.XMPL_SCHLIB(SCH_1)AGE1_I0_RESISTOR_DEFA~
ULT@SCHLIB.RESISTOR(CHIPS)
Property Name: VALUE
Property Value:
***********************************************
* End assigning physical parts. (00:00:00) *
***********************************************
***************
* Packaging *
***************
*******************************
* End packaging (00:00:00) *
*******************************
1 errors detected
No warnings detected
Start time 10:35:30
End time 10:35:30
Elapsed time 0:00:00
*********************************************
* ERROR Packager-XL exiting with status 1 *
*********************************************
______ end pxl.log ______
schlib :: For pack_type 'DEFAULT' : Netrev Reported error.
netrev.log follows...
______ start netrev.log ______
Cadence Design Systems, Inc. netrev 15.2 Fri Jul 06 10:35:35 2007
(C) Copyright 2002 Cadence Design Systems, Inc.
------ Directives ------
RIPUP_ETCH FALSE;
RIPUP_SYMBOLS ALWAYS;
MISSING SYMBOL AS ERROR TRUE;
SCHEMATIC_DIRECTORY 'E:\cadwork\low_doctor\temp\temp_ftb_test\xmpllib\xmpl_schlib\packaged';
BOARD_DIRECTORY '';
OLD_BOARD_NAME 'E:\cadwork\low_doctor\temp\temp_ftb_test\xmpllib\xmpl_schlib\physical\libtest.brd';
NEW_BOARD_NAME 'processed.brd';
CmdLine: netrev -proj xmpl_schlib.cpm -e -5 -y 1 libtest.brd E:\cadwork\low_doctor\temp\temp_ftb_test/xmpllib\xmpl_schlib\physical/processed.brd
------ Preparing to read pst files ------
Starting to read E:/cadwork/low_doctor/temp/temp_ftb_test/xmpllib/xmpl_schlib/packaged/pstchip.dat
Finished reading E:/cadwork/low_doctor/temp/temp_ftb_test/xmpllib/xmpl_schlib/packaged/pstchip.dat (00:00:00.03)
Starting to read E:/cadwork/low_doctor/temp/temp_ftb_test/xmpllib/xmpl_schlib/packaged/pstxprt.dat
Finished reading E:/cadwork/low_doctor/temp/temp_ftb_test/xmpllib/xmpl_schlib/packaged/pstxprt.dat (00:00:00.00)
Starting to read E:/cadwork/low_doctor/temp/temp_ftb_test/xmpllib/xmpl_schlib/packaged/pstxnet.dat
Finished reading E:/cadwork/low_doctor/temp/temp_ftb_test/xmpllib/xmpl_schlib/packaged/pstxnet.dat (00:00:00.01)
------ Oversights/Warnings/Errors ------
#1 ERROR(305) Device/Symbol check error detected.
Symbol 'DIP2' for device 'RESISTOR' not found in PSMPATH or must be "dbdoctor"ed.
------ Library Paths ------
MODULEPATH = .
d:\Cadence\SPB_15.2\share\local\pcb/modules
PSMPATH = E:/cadwork/psmlib
E:/cadwork/low_doctor
E:/cadwork/low_doctor/symbols
E:/cadwork
E:/cadwork/symbols
d:/Cadence/SPB_15.2/share/local/pcb/symbols
d:/Cadence/SPB_15.2/share/pcb/pcb_lib/symbols
d:/Cadence/SPB_15.2/share/pcb/allegrolib/symbols
PADPATH = E:\cadwork\padlib\
.
symbols
..
../symbols
d:\Cadence\SPB_15.2\share\local\pcb/padstacks
d:\Cadence\SPB_15.2\share\pcb/pcb_lib/symbols
d:\Cadence\SPB_15.2\share\pcb/allegrolib/symbols
------ Summary Statistics ------
#2 ERROR(102) Run stopped because errors were detected
netrev run on Jul 6 10:35:35 2007
DESIGN NAME : 'XMPL_SCHLIB'
PACKAGING ON 06-Jul-2007 AT 10:35:30
COMPILE 'logic'
CHECK_PIN_NAMES OFF
CROSS_REFERENCE OFF
DIRECTORIES <none>
FEEDBACK OFF
INCREMENTAL OFF
INTERFACE_TYPE PHYSICAL
LIBRARIES 'schlib' 'xmpllib' 'standard'
MASTER_LIBRARIES <none>
MAX_ERRORS 500
MERGE_MINIMUM 5
NET_NAME_CHARS '#%&()*+-./:=>?@[]^_`|'
NET_NAME_LENGTH 24
OVERSIGHTS ON
REPLACE_CHECK OFF
SINGLE_NODE_NETS ON
SPLIT_MINIMUM 0
SUPPRESS 20
WARNINGS ON
2 errors detected
No oversight detected
No warning detected
cpu time 0:00:18
elapsed time 0:00:00
______ end netrev.log ______
schlib :: Test FAILED
______ start ptf.log _____
DEFAULT:: Injected Property clash in selected ptfs in part RESISTOR
______ end ptf.log ______
没人理俺啊,着急啊
是不是PCB线路图的封装的孔不存在呀
检查一下
写错了,是不是PCB线路图的封装的PIN不存在呀
按它给提示找找
"Symbol 'DIP2' for device 'RESISTOR' not found in PSMPATH or must be "dbdoctor"ed."
能不能把你做的發過來看一看,或許會更清楚一點!好回答你的問題!