导出网表出的错误,帮帮忙!
#1 Warning [ALG0047] "No_connect" property on Pin "U58.12" ignored for U58: SCHEMATIC1, SHEET28 - AIC32 (2.50, 6.50). Connecting pin to net "GND".
#2 Warning [ALG0047] "No_connect" property on Pin "U58.11" ignored for U58: SCHEMATIC1, SHEET28 - AIC32 (2.50, 6.50). Connecting pin to net "GND".
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#84 Warning [ALG0016] Part Name "CAP 100NF CERMC 16V 10% 603_EIA0402_5.6PF" is renamed to "CAP 100NF CERMC 16V 10% 603_EIA".
#85 Warning [ALG0016] Part Name "CAPACITOR POL_1_EIA1206P_10UF 6.3V" is renamed to "CAPACITOR POL_1_EIA1206P_10UF 6".
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Scanning netlist files ...
Loading... F:\CADENCESTUDY\6467\SCH\NETLIST/pstchip.dat
Loading... F:\CADENCESTUDY\6467\SCH\NETLIST/pstchip.dat
Loading... F:\CADENCESTUDY\6467\SCH\NETLIST/pstxprt.dat
Loading... F:\CADENCESTUDY\6467\SCH\NETLIST/pstxnet.dat
ERROR(SPCODD-413):
Error at line 1131 in file F:\CADENCESTUDY\6467\SCH\NETLIST/pstxnet.dat. Ref
erence designators inconsistent in xprt and xnet files. Reference Designator in xprt file: U21. Reference Designator in xnet file: U63. Schematic Instance davincihd_evm_orcad_revf.schematic1(sch_1):ins16664498@\505962\.\sn74lvc1gu04_9.normal\(chips) (MODULE: DAVINCIHD_EVM_ORCAD_REVF; PART: SN74LVC1GU04_9).
ERROR(SPCODD-383): Error at line 1131 in file F:\CADENCESTUDY\6467\SCH\NETLIST/pstxnet.dat. Error loading the net list file
#146 Error [ALG0036] Unable to read logical netlist data.
Exiting... "F:\Cadence\SPB_16.2\tools\capture\pstswp.exe" -pst -d "f:\cadencestudy\6467\sch\davincihd_evm_orcad_revf.dsn" -n "F:\CADENCESTUDY\6467\SCH\NETLIST" -c "F:\Cadence\SPB_16.2\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint"
*** Done ***
请教这里的No_connect和Part Name 怎么解决?还有最后面的Error at line 1131 错误是什么意思?
请高手帮帮忙!
前一个错误,有两种情况1.>封装PIN与原理图PIN对应有误 2.>No_connect表示你还有未连接的pin,Part Name 名称长了。
后一个错误,本人没分页布局过,从英文的意思推测,在原理图中选中了按页布局,但有个网络需作Xnet作等长,这个等长夹的元件正好跨越在两页中! 不知道我说的对不对?
ls,先谢谢帮忙!
前两个warning的问题都解决了,但是后面那个没解决
我好像没有选按页布局啊,Xnet等长在原理图里设置的吗?
好像不是这样!~~~~~无奈啊
Xnet等长设置是在Allegro里的,xprt 和xnet不一致呀!看看u21和u63设置是不是有问题!
路过。支持下