Allegro 16.5发布

哇塞~ 時代一直在進步呀！

诶，公司还在用15.5……

真的假的，这个也太快了啊

关注一下，期待中！

http://www.cadence.com/cadence/n ... /Pages/allegro.aspx
New Allegro 16.5 Technology
On May 23, 2011 Cadence will release the 16.5 version of its Allegro PCB and IC packaging technology, providing customers with new capabilities for a shorter, predictable, and convergent path to product creation. The latest Allegro technology will be available through flexible on-demand product configurations that offer cost-efficiency and scalability. Allegro 16.5 spans silicon, SoC, and system-level development and offers PCB designers benefits such as:
    * Higher functional density with a constraint-driven flow for embedded components
    * Faster timing closure with new PCB interconnect design planning technology
    * Fewer physical prototype iterations with concurrent team design authoring
    * More efficient low-power design with integrated power delivery network analysis
    * A compliant and faster implementation path with package/board-aware SoC IP
    * Smoother collaboration among global teams with new SiP distributed co-design
    * Flexibility through “base plus options” configurations

期待中。

Allegro 16.5 Powers up Allegro PCB PDN Analysis
By Team Allegro on April 29, 2011
Comments(0)
Filed under: PDN, Power, PCB SI, PCB Signal integrity, Power Delivery Network, power integrity, PCB power integrity, Allegro 16.5
Attendees of DesignCon 2011 received a sneak peek, and now Allegro PCB designers can officially check out a new power delivery network (PDN) analysis solution as part of the Allegro 16.5 release

有什么 改进呢！

刚刚安装了16.3还没学会使用呢………………

已下载安装～～～

good   good   good   good

一味地加新功能，而不把之前版本的BUG修正，我觉得升级没啥意义~~

一味地加新功能，而不把之前版本的BUG修正，我觉得升级没啥意义~~