微波EDA网,见证研发工程师的成长!
首页 > 研发问答 > PCB设计问答 > Cadence Allegro > net-in时出现同一种错误

net-in时出现同一种错误

时间:10-02 整理:3721RD 点击:

本来正做一块仪器四层板,net-in时总会出错,错误信息如下:

ERROR: Expected ';' , found an illegal character, line ignored.
-------------------------------------------------------------------------------
     R993.2 C885.2 R898.2 C855.2,
           ^
ERROR: Expected ';' , found an illegal character, line ignored.
-------------------------------------------------------------------------------
     U848.4 U847.4 U819.1 R965.2,
           ^
ERROR: Expected ';' , found an illegal character, line ignored.
-------------------------------------------------------------------------------
     Q810.3 C854.2 R917.2 U832.1,
           ^
ERROR: Expected ';' , found an illegal character, line ignored.
-------------------------------------------------------------------------------
     C874.2 C888.2 C871.2 C848.2,
           ^
ERROR: Expected ';' , found an illegal character, line ignored.
-------------------------------------------------------------------------------
     Q819.3 R978.2 Q813.3 R969.2,
           ^
ERROR: Expected ';' , found an illegal character, line ignored.
-------------------------------------------------------------------------------
     R977.2 Q818.3 U833.1 U853.4,
           ^
ERROR: Expected ';' , found an illegal character, line ignored.
-------------------------------------------------------------------------------
     U805.1 U854.4 C826.2 C847.2,
           ^
ERROR: Expected ';' , found an illegal character, line ignored.
-------------------------------------------------------------------------------
     R900.2 U820.1 R893.2 C803.2,
           ^
ERROR: Expected ';' , found an illegal character, line ignored.
-------------------------------------------------------------------------------
     Q811.3 R967.2 C849.2 R990.2,
           ^
ERROR: Expected ';' , found an illegal character, line ignored.
-------------------------------------------------------------------------------

请高手指点

看一下你netfile, ';'前面有非法字符啊,仔细检查一下,改过来肯定能netin进去,这是很常见的错误了,画线路图时填footprint很容易带上一些空格等的非法字符上去。

已经解决了,多谢指点

Copyright © 2017-2020 微波EDA网 版权所有

网站地图

Top