求助:FPGA IO PIN 在pcb中 swap pin完，回注原理图时出错啦！

在原理图中的fpga 其io分为了两个part，netlist到pcb后，在swap pin后，要回注到原理图，

但是在第二次回注时出错：

Spawning... "D:\Projects\Cadence\SPB_15.5.1\tools\capture\pstswp.exe" -pst -d "D:\Projects\LMTTC\BigDipper\07-02-05\sch\001.dsn" -n "D:\PROJECTS\LMTTC\BIGDIPPER\07-02-05\SCH\ALLEGRO" -c "D:\Projects\Cadence\SPB_15.5.1\tools\capture\MY_allegro.cfg" -v 3 -j "PCB Footprint"
#1 Error   [ALG0045] multiple pin U3's which have different nets connected for U13: FPGA_BLOCK, IO2 (195.58, 17.78).
              Check for incorrect packaging of all devices in U13.
#2 Aborting Netlisting... Please correct the above errors and retry.

Exiting... "D:\Projects\Cadence\SPB_15.5.1\tools\capture\pstswp.exe" -pst -d "D:\Projects\LMTTC\BigDipper\07-02-05\sch\001.dsn" -n "D:\PROJECTS\LMTTC\BIGDIPPER\07-02-05\SCH\ALLEGRO" -c "D:\Projects\Cadence\SPB_15.5.1\tools\capture\MY_allegro.cfg" -v 3 -j "PCB Footprint"

我发现原理图中在第一次回注时产生了两个u13引脚，第二次回注时所以出错，

问：是第一次回注时swap pin的结果没有正确回注，如何解决?