时钟脉冲的Verilog程序，但是编译总是无法通过
时间：10-02
整理：3721RD
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基于ise14.7
下面是一个时钟脉冲的Verilog程序，但是编译总是无法通过，检查也检查不出问题，求大神赐教！
module clock_pulse(
input wire inp,
input wire cclk,
input wire clr,
output wire outp
);
reg delay1;
reg delay2;
reg delay3;
always@(posedge cclk or negedge clr)
begin
if(clr==1'b1)
begin
delay1 missing in the sensitivity list is added for synthesis purposes. HDL and post-synthesis simulations may differ as a result.
WARNING:HDLCompiler:1499 - "E:\ISE-FPGA Procedure\clock_pulse\clock_pulse.v" Line 21: Empty module remains a black box.
下面是一个时钟脉冲的Verilog程序，但是编译总是无法通过，检查也检查不出问题，求大神赐教！
module clock_pulse(
input wire inp,
input wire cclk,
input wire clr,
output wire outp
);
reg delay1;
reg delay2;
reg delay3;
always@(posedge cclk or negedge clr)
begin
if(clr==1'b1)
begin
delay1 missing in the sensitivity list is added for synthesis purposes. HDL and post-synthesis simulations may differ as a result.
WARNING:HDLCompiler:1499 - "E:\ISE-FPGA Procedure\clock_pulse\clock_pulse.v" Line 21: Empty module remains a black box.
确实是被多个时钟沿驱动，这里不允许的情况下，你可以尝试将边沿触发改为电平触发
参考Xilinx官网：http://forums.xilinx.com/t5/Synt ... rted-for/td-p/68133
很明显你的异步复位没写对！改为if（clr==1’b0）就可以了