好久没发帖，SIlist话题之PCB的损耗可否预测？
时间：10-02
整理：3721RD
点击：
故事是这样开始的：有人问树脂含量和损耗的关系。
Date: Tue, 30 Oct 2012 08:52:23 +0800 (CST)
Hello experts,
>
> I'm from PCB house. Recently we have producted some insertion loss test
> boards(16L, SET2DIL coupon, IS415/IT150DA/I-Speed Mid/low loss material with
> RTF copper foil). We found that the multiply core and high resin PP will
> result a lower loss result. It's a trouble to MI engineer. I would like to
> know how to predict the loss base on stackup. Please help to suggest (papers,
> script, free software etc ). Thanks a lot！
>
>
>
> Best regards,
>
> Terry Ho
然后 Scott McMorrow ,steve weir,Loyer Jeff 这些活跃分子开始依次发表意见.
From: Scott McMorrow <scott@xxxxxxxxxxxxx>
Date: Mon, 29 Oct 2012 21:02:36 -0400
Hmmm... I'm in the middle of the middle of Hurricane Sandy. Power is out.
Storm surge is causing the river across the street to rise to unprecedented
levels.
... and this guy wants us to do his job and suggest free software.
From: steve weir <weirsi@xxxxxxxxxx>
Date: Mon, 29 Oct 2012 21:23:22 -0700
As a PCB fabricator I think you need to develop in-house material
properties expertise. Your competitors who understand the materials
they use and their process limits are positioned to get higher yield
percentages at lower cost because of their knowledge.
I appreciate that you don't want to spend unnecessary money, but at
least spend the time to learn about what you are using. I am troubled
that your engineer knows so little about the materials you use that he
is surprised by common results. Once your company understands materials
better you may well appreciate the value of commercial stack-up planning
software.
Steve.
From: "Loyer, Jeff" <jeff.loyer@xxxxxxxxx>
Date: Wed, 31 Oct 2012 21:33:48 +0000
I'm surprised at the tone of the responses to this posting (but perhaps I
shouldn't be, unfortunately); I don't see anything untoward in it. I would
like to provide some context (with some assumptions on my part) for the message
lest other innocent postings meet with similar fates. I'll also (eventually)
provide my answer to the question, as I understand it.
There is a significant portion (majority?) of the industry which is extremely
cost constrained. For instance, to them rotating a design 10 degrees is
impractical, much less 22 or 45 degrees. Thus, they find other cost-effective
yet effective means of solving problems (such as zig-zag routing), even though
those don't appear efficient to others to whom cost is not an issue.
There are new pressures being applied to this segment - designers are now not
only requiring impedance control, but are also insisting on insertion loss
control. This is a HUGE paradigm shift, very similar to what we encountered
when traceable impedance control was first introduced. That was a very
challenging evolution, and this will be also.
As an example, PCB vendors are now being advised to smooth their copper, after
years of purposely roughening it for best mechanical integrity. It should come
as no surprise that this is not a trivial change, considering the effort that
has gone into ensuring mechanically robust designs.
Likewise, many other basic assumptions that we've been able to apply for years
are now being drawn into question, and PCB vendors are looking for help to
intelligently and cost-effectively explore options - "How much effect does
rougher copper have on insertion loss?". I believe Terry is highlighting the
fact that, while there are many tools available for impedance prediction,
insertion loss modeling is much less accessible. I don't think it is
inappropriate to ask if there are cost-effective, reliable tools available to
predict insertion loss based on a proposed stackup.
Unfortunately, I believe the answer to the question is that there are no
reliable, cheap (~free) modelers available to predict insertion loss. And, the
ones that are available require a great deal more knowledge about the stackup
than impedance modeling does, and that information is not easily obtained.
There are some of us working with a vendor to test their modeler against a
variety of stackups and we'll present results at DesignCon. My personal goal
is not so much to test a specific modeler but to judge how effective a modeler
can be given information that can reasonably be gleaned prior to building with
various materials, copper types, etc.
In the absence of a modeling tool, or in addition to one, I believe empirical
data is the best predictor of insertion loss. To do this, however, you have to
build a stackup representing the final design, and it's not clear at this point
how broadly you can extrapolate those results to other stackups. But, I know
many material vendors and PCB shops are engaged in similar efforts.
I think this is very similar to what we went through with impedance control -
the shops which most quickly were able to predict and control that
characteristic had an advantage. I think successful PCB vendors will need
reliable modeling software and empirical data on insertion loss for their
particular choices of materials, etc. - they will be able to find the most cost
effective solution.
Bottom line: I doubt a reliable modeling tool is going to be cheap, but is
going to be necessary, and you'll want to compare any tool you do purchase
against empirical data before you trust it.
I hope this helps,
Jeff Loyer
From: steve weir <weirsi@xxxxxxxxxx>
Date: Wed, 31 Oct 2012 20:14:41 -0700
Jeff, given that the only two responses were Scott and mine, I am
surprised that you are disappointed with both.
In a fabrication market filled with intense competition it is up to
individual players to keep up with the technology requirements of the
market or get left behind. The task is not simple. Depending on how far
up the frequency range one needs to go, dialing in cost effective
process requires substantial skills, time, effort and serious money. It
represents competitive advantage to OEMs and their partner pcb fab
houses alike. Neither who have invested are likely to hand over that
kind of advantage especially when it is so costly to obtain.
I don't mind that Terry is looking for a solution on the cheap or free.
If one could obtain such a sweet deal, one would be foolish not to take
it. I am troubled that in this day in age, his organization hopes to
address a sophisticated issue before his technical staff has a grip on
the basics. I fail to understand what you find inappropriate about
that concern. I would rather yell at someone headed for a cliff to stop
than smile and wave.
Best Regards,
Steve.
From: "Loyer, Jeff" <jeff.loyer@xxxxxxxxx>
Date: Fri, 2 Nov 2012 15:37:46 +0000
I realized we hadn't answered the basic question - "why does a high resin
prepreg give lower loss?" The prediction of loss vs. resin content isn't
trivial; as Steve said, a tool which allows you to model loss for the various
scenarios should be on your Christmas wish list. Here are the factors that I
know of (thanks to Richard Kunze for clarifying things for me, and I welcome
others' data/opinions):
* Resin has a lower Er than glass
* loss is approximately proportional to Df * sqrt(Er), so lowering Er
lowers loss
* lower Er allows wider traces for the same impedance - this may decrease
loss also
* But, resin is more lossy than glass, so Df may increase
* for standard FR4 constructions, this is especially true. The data sheet
for IS370HR, for instance, shows Df varying from 0.0177 to 0.0247 (1GHz),
depending on the resin content
* for low loss materials, this doesn't hold. The data sheet for Meg6
shows Df constant (0.002 @ 1GHz) for all its flavors of prepreg
* Where the factors dominate will depend on your relative conductor vs.
dielectric loss effects: for FR4, dielectric loss dominates at >~1GHz; for
low-loss materials, conductor loss dominates up to much higher frequencies (as
much as 10GHz).
In your particular (low loss) case, the lower Er of the resin-rich case is
trumping the Df change (or lack of) so you get lower loss.
Only a tool which takes into account the properties of the specific material
under consideration can be expected to give an accurate prediction of insertion
loss for various resin contents.
There are also environmental effects (I haven't heard or seen these stressed at
this point, though that may change soon):
* Higher resin content will absorb more moisture, and thus your loss will be
more susceptible to humidity effects
* There's a difference in how the various materials' Df changes w/ temperature
- more at DesignCon
I hope this helps,
Jeff Loyer
From: Scott McMorrow <scott@xxxxxxxxxxxxx>
Date: Thu, 8 Nov 2012 09:12:46 -0500
Jeff
A few quick comments. Although the tanD of Meg 6 is stated to be flat, it
is not if you measure it. The manufacturer reported characterization in
the data sheet is not correct. Causality is violated when tanD is flat.
Loss is generally due to molecular dipole losses in the material. It can
be low for high Er, as is the case with ceramic.
Hygroscopic loss is due to molecular polarity. Polar molecules "glom" on to
water molecules, which are also polar. Same property makes the material
extremely "sticky."
The paper that Jason Miller of Oracle and I wrote for DesignCon last year
covers some of the impact of temperature and humidity on measured losses.
I don't have access to my storage server right now, otherwise I'd give a
paper citation.
regards,
Scott
From: Kirby Goulet <kgoulet@xxxxxxxx>
Date: Fri, 9 Nov 2012 11:08:49 -0800 (PST)
It's not production quality software but you could try the mdtlc calculator to
experiment. I tried Jeff's example and it seems to point to an explanation.
The source code is available so you might extend it to do what you want if you
have more time than money.
It looks like a race between loss due to increasing loss due to resin and
decreasing loss due to wider traces. There is a bigger increase in the resin
content for the IS370 case over the IS415 case. Not only that, but the IS370
resin is lossier: 0.0169 versus 0.02984 so the winner is increasing loss.
From the field solver,
IS370: the effective dielectric loss went up 14.7%. The perimeter of the
conductor went up 3.6%.
IS415: the effective dielectric loss went up 6.7%. The perimeter of the
conductor went up 5.7%.
In the second case, overall dielectric loss is a smaller fraction than the
first case. The missing bit of information you need to add is the conductor
loss.
INPUT PARAMETERS:
Layer Thick Specifications
Copper Plane Top 1.30 Opening w=0.0 offset=0.0
Laminate Layer 1 3.90 Resin Content 57.0% 3.4-4.9
Signal Layer 1 1.20 4.3-7.2-4.3 Etchback=0.00
Laminate Layer 2 3.90 Resin Content 57.0% 3.4-4.9
Copper Plane Bottom 1.30 Opening w=0.0 offset=0.0
Layer Thick Er Loss Tangent
Copper Plane Top 1.30 3.20
Laminate Layer 1 3.90 4.02 0.02100
Signal Layer 1 1.20 3.38 0.02984
Laminate Layer 2 3.90 4.02 0.02100
Copper Plane Bottom 1.30 3.20
DC resistance by dimensions:
Rdc_trace_1= 131.53 Rdc_trace_2 = 131.53 milliohms/in 20C
DC resistance by pixel count:
Rdc_trace_1= 131.531 Rdc_trace_2 = 131.531 milliohm/in
C_odd = 4.221 pF/in C_even = 3.968 pF/in
Er_odd = 3.923 Er_even = 3.947
Loss_tan_o = 0.02212 Loss_tan_e = 0.02184
Delay_odd = 167.801 Delay_even = 168.314 ps/in.
Z_diff = 79.501 ohms Z_comm = 21.209 ohms
Simulation pix map 122 pixels high by 800 pixels wide.
293824 bytes allocated for bmp.
INPUT PARAMETERS:
Layer Thick Specifications
Copper Plane Top 1.30 Opening w=0.0 offset=0.0
Laminate Layer 1 4.20 Resin Content 75.0% 3.4-4.9
Signal Layer 1 1.20 4.5-7.0-4.5 Etchback=0.00
Laminate Layer 2 4.20 Resin Content 75.0% 3.4-4.9
Copper Plane Bottom 1.30 Opening w=0.0 offset=0.0
Layer Thick Er Loss Tangent
Copper Plane Top 1.30 3.20
Laminate Layer 1 4.20 3.75 0.02470
Signal Layer 1 1.20 3.38 0.02984
Laminate Layer 2 4.20 3.75 0.02470
Copper Plane Bottom 1.30 3.20
DC resistance by dimensions:
Rdc_trace_1= 125.69 Rdc_trace_2 = 125.69 milliohms/in 20C
DC resistance by pixel count:
Rdc_trace_1= 125.685 Rdc_trace_2 = 125.685 milliohm/in
C_odd = 3.929 pF/in C_even = 3.624 pF/in
Er_odd = 3.694 Er_even = 3.710
Loss_tan_o = 0.02537 Loss_tan_e = 0.02518
Delay_odd = 162.844 Delay_even = 163.195 ps/in.
Z_diff = 82.900 ohms Z_comm = 22.519 ohms
Log file save name:
mdtlc_12100946383.txt
Simulation pix map 118 pixels high by 780 pixels wide.
277144 bytes allocated for bmp.
INPUT PARAMETERS:
Layer Thick Specifications
Copper Plane Top 1.30 Opening w=0.0 offset=0.0
Laminate Layer 1 4.00 Resin Content 45.0% 2.6-5.1
Signal Layer 1 1.20 4.1-7.4-4.1 Etchback=0.00
Laminate Layer 2 4.00 Resin Content 45.0% 2.6-5.1
Copper Plane Bottom 1.30 Opening w=0.0 offset=0.0
Layer Thick Er Loss Tangent
Copper Plane Top 1.30 3.20
Laminate Layer 1 4.00 3.98 0.01140
Signal Layer 1 1.20 2.64 0.01690
Laminate Layer 2 4.00 3.98 0.01140
Copper Plane Bottom 1.30 3.20
DC resistance by dimensions:
Rdc_trace_1= 137.95 Rdc_trace_2 = 137.95 milliohms/in 20C
DC resistance by pixel count:
Rdc_trace_1= 137.947 Rdc_trace_2 = 137.947 milliohm/in
C_odd = 3.910 pF/in C_even = 3.695 pF/in
Er_odd = 3.769 Er_even = 3.817
Loss_tan_o = 0.01202 Loss_tan_e = 0.01189
Delay_odd = 164.490 Delay_even = 165.524 ps/in.
Z_diff = 84.134 ohms Z_comm = 22.396 ohms
Simulation pix map 118 pixels high by 795 pixels wide.
282454 bytes allocated for bmp.
INPUT PARAMETERS:
Layer Thick Specifications
Copper Plane Top 1.30 Opening w=0.0 offset=0.0
Laminate Layer 1 4.00 Resin Content 54.0% 2.6-5.1
Signal Layer 1 1.20 4.4-7.1-4.4 Etchback=0.00
Laminate Layer 2 4.00 Resin Content 54.0% 2.6-5.1
Copper Plane Bottom 1.30 Opening w=0.0 offset=0.0
Layer Thick Er Loss Tangent
Copper Plane Top 1.30 3.20
Laminate Layer 1 4.00 3.76 0.01230
Signal Layer 1 1.20 2.64 0.01690
Laminate Layer 2 4.00 3.76 0.01230
Copper Plane Bottom 1.30 3.20
DC resistance by dimensions:
Rdc_trace_1= 128.54 Rdc_trace_2 = 128.54 milliohms/in 20C
DC resistance by pixel count:
Rdc_trace_1= 128.542 Rdc_trace_2 = 128.542 milliohm/in
C_odd = 3.865 pF/in C_even = 3.623 pF/in
Er_odd = 3.588 Er_even = 3.631
Loss_tan_o = 0.01283 Loss_tan_e = 0.01270
Delay_odd = 160.480 Delay_even = 161.455 ps/in.
Z_diff = 83.041 ohms Z_comm = 22.280 ohms
看完之后，我有一事不明，我总是分不清奇偶，不知道这两者到底如何区分，亲，你能告诉我吗?
Date: Tue, 30 Oct 2012 08:52:23 +0800 (CST)
Hello experts,
>
> I'm from PCB house. Recently we have producted some insertion loss test
> boards(16L, SET2DIL coupon, IS415/IT150DA/I-Speed Mid/low loss material with
> RTF copper foil). We found that the multiply core and high resin PP will
> result a lower loss result. It's a trouble to MI engineer. I would like to
> know how to predict the loss base on stackup. Please help to suggest (papers,
> script, free software etc ). Thanks a lot！
>
>
>
> Best regards,
>
> Terry Ho
然后 Scott McMorrow ,steve weir,Loyer Jeff 这些活跃分子开始依次发表意见.
From: Scott McMorrow <scott@xxxxxxxxxxxxx>
Date: Mon, 29 Oct 2012 21:02:36 -0400
Hmmm... I'm in the middle of the middle of Hurricane Sandy. Power is out.
Storm surge is causing the river across the street to rise to unprecedented
levels.
... and this guy wants us to do his job and suggest free software.
From: steve weir <weirsi@xxxxxxxxxx>
Date: Mon, 29 Oct 2012 21:23:22 -0700
As a PCB fabricator I think you need to develop in-house material
properties expertise. Your competitors who understand the materials
they use and their process limits are positioned to get higher yield
percentages at lower cost because of their knowledge.
I appreciate that you don't want to spend unnecessary money, but at
least spend the time to learn about what you are using. I am troubled
that your engineer knows so little about the materials you use that he
is surprised by common results. Once your company understands materials
better you may well appreciate the value of commercial stack-up planning
software.
Steve.
From: "Loyer, Jeff" <jeff.loyer@xxxxxxxxx>
Date: Wed, 31 Oct 2012 21:33:48 +0000
I'm surprised at the tone of the responses to this posting (but perhaps I
shouldn't be, unfortunately); I don't see anything untoward in it. I would
like to provide some context (with some assumptions on my part) for the message
lest other innocent postings meet with similar fates. I'll also (eventually)
provide my answer to the question, as I understand it.
There is a significant portion (majority?) of the industry which is extremely
cost constrained. For instance, to them rotating a design 10 degrees is
impractical, much less 22 or 45 degrees. Thus, they find other cost-effective
yet effective means of solving problems (such as zig-zag routing), even though
those don't appear efficient to others to whom cost is not an issue.
There are new pressures being applied to this segment - designers are now not
only requiring impedance control, but are also insisting on insertion loss
control. This is a HUGE paradigm shift, very similar to what we encountered
when traceable impedance control was first introduced. That was a very
challenging evolution, and this will be also.
As an example, PCB vendors are now being advised to smooth their copper, after
years of purposely roughening it for best mechanical integrity. It should come
as no surprise that this is not a trivial change, considering the effort that
has gone into ensuring mechanically robust designs.
Likewise, many other basic assumptions that we've been able to apply for years
are now being drawn into question, and PCB vendors are looking for help to
intelligently and cost-effectively explore options - "How much effect does
rougher copper have on insertion loss?". I believe Terry is highlighting the
fact that, while there are many tools available for impedance prediction,
insertion loss modeling is much less accessible. I don't think it is
inappropriate to ask if there are cost-effective, reliable tools available to
predict insertion loss based on a proposed stackup.
Unfortunately, I believe the answer to the question is that there are no
reliable, cheap (~free) modelers available to predict insertion loss. And, the
ones that are available require a great deal more knowledge about the stackup
than impedance modeling does, and that information is not easily obtained.
There are some of us working with a vendor to test their modeler against a
variety of stackups and we'll present results at DesignCon. My personal goal
is not so much to test a specific modeler but to judge how effective a modeler
can be given information that can reasonably be gleaned prior to building with
various materials, copper types, etc.
In the absence of a modeling tool, or in addition to one, I believe empirical
data is the best predictor of insertion loss. To do this, however, you have to
build a stackup representing the final design, and it's not clear at this point
how broadly you can extrapolate those results to other stackups. But, I know
many material vendors and PCB shops are engaged in similar efforts.
I think this is very similar to what we went through with impedance control -
the shops which most quickly were able to predict and control that
characteristic had an advantage. I think successful PCB vendors will need
reliable modeling software and empirical data on insertion loss for their
particular choices of materials, etc. - they will be able to find the most cost
effective solution.
Bottom line: I doubt a reliable modeling tool is going to be cheap, but is
going to be necessary, and you'll want to compare any tool you do purchase
against empirical data before you trust it.
I hope this helps,
Jeff Loyer
From: steve weir <weirsi@xxxxxxxxxx>
Date: Wed, 31 Oct 2012 20:14:41 -0700
Jeff, given that the only two responses were Scott and mine, I am
surprised that you are disappointed with both.
In a fabrication market filled with intense competition it is up to
individual players to keep up with the technology requirements of the
market or get left behind. The task is not simple. Depending on how far
up the frequency range one needs to go, dialing in cost effective
process requires substantial skills, time, effort and serious money. It
represents competitive advantage to OEMs and their partner pcb fab
houses alike. Neither who have invested are likely to hand over that
kind of advantage especially when it is so costly to obtain.
I don't mind that Terry is looking for a solution on the cheap or free.
If one could obtain such a sweet deal, one would be foolish not to take
it. I am troubled that in this day in age, his organization hopes to
address a sophisticated issue before his technical staff has a grip on
the basics. I fail to understand what you find inappropriate about
that concern. I would rather yell at someone headed for a cliff to stop
than smile and wave.
Best Regards,
Steve.
From: "Loyer, Jeff" <jeff.loyer@xxxxxxxxx>
Date: Fri, 2 Nov 2012 15:37:46 +0000
I realized we hadn't answered the basic question - "why does a high resin
prepreg give lower loss?" The prediction of loss vs. resin content isn't
trivial; as Steve said, a tool which allows you to model loss for the various
scenarios should be on your Christmas wish list. Here are the factors that I
know of (thanks to Richard Kunze for clarifying things for me, and I welcome
others' data/opinions):
* Resin has a lower Er than glass
* loss is approximately proportional to Df * sqrt(Er), so lowering Er
lowers loss
* lower Er allows wider traces for the same impedance - this may decrease
loss also
* But, resin is more lossy than glass, so Df may increase
* for standard FR4 constructions, this is especially true. The data sheet
for IS370HR, for instance, shows Df varying from 0.0177 to 0.0247 (1GHz),
depending on the resin content
* for low loss materials, this doesn't hold. The data sheet for Meg6
shows Df constant (0.002 @ 1GHz) for all its flavors of prepreg
* Where the factors dominate will depend on your relative conductor vs.
dielectric loss effects: for FR4, dielectric loss dominates at >~1GHz; for
low-loss materials, conductor loss dominates up to much higher frequencies (as
much as 10GHz).
In your particular (low loss) case, the lower Er of the resin-rich case is
trumping the Df change (or lack of) so you get lower loss.
Only a tool which takes into account the properties of the specific material
under consideration can be expected to give an accurate prediction of insertion
loss for various resin contents.
There are also environmental effects (I haven't heard or seen these stressed at
this point, though that may change soon):
* Higher resin content will absorb more moisture, and thus your loss will be
more susceptible to humidity effects
* There's a difference in how the various materials' Df changes w/ temperature
- more at DesignCon
I hope this helps,
Jeff Loyer
From: Scott McMorrow <scott@xxxxxxxxxxxxx>
Date: Thu, 8 Nov 2012 09:12:46 -0500
Jeff
A few quick comments. Although the tanD of Meg 6 is stated to be flat, it
is not if you measure it. The manufacturer reported characterization in
the data sheet is not correct. Causality is violated when tanD is flat.
Loss is generally due to molecular dipole losses in the material. It can
be low for high Er, as is the case with ceramic.
Hygroscopic loss is due to molecular polarity. Polar molecules "glom" on to
water molecules, which are also polar. Same property makes the material
extremely "sticky."
The paper that Jason Miller of Oracle and I wrote for DesignCon last year
covers some of the impact of temperature and humidity on measured losses.
I don't have access to my storage server right now, otherwise I'd give a
paper citation.
regards,
Scott
From: Kirby Goulet <kgoulet@xxxxxxxx>
Date: Fri, 9 Nov 2012 11:08:49 -0800 (PST)
It's not production quality software but you could try the mdtlc calculator to
experiment. I tried Jeff's example and it seems to point to an explanation.
The source code is available so you might extend it to do what you want if you
have more time than money.
It looks like a race between loss due to increasing loss due to resin and
decreasing loss due to wider traces. There is a bigger increase in the resin
content for the IS370 case over the IS415 case. Not only that, but the IS370
resin is lossier: 0.0169 versus 0.02984 so the winner is increasing loss.
From the field solver,
IS370: the effective dielectric loss went up 14.7%. The perimeter of the
conductor went up 3.6%.
IS415: the effective dielectric loss went up 6.7%. The perimeter of the
conductor went up 5.7%.
In the second case, overall dielectric loss is a smaller fraction than the
first case. The missing bit of information you need to add is the conductor
loss.
INPUT PARAMETERS:
Layer Thick Specifications
Copper Plane Top 1.30 Opening w=0.0 offset=0.0
Laminate Layer 1 3.90 Resin Content 57.0% 3.4-4.9
Signal Layer 1 1.20 4.3-7.2-4.3 Etchback=0.00
Laminate Layer 2 3.90 Resin Content 57.0% 3.4-4.9
Copper Plane Bottom 1.30 Opening w=0.0 offset=0.0
Layer Thick Er Loss Tangent
Copper Plane Top 1.30 3.20
Laminate Layer 1 3.90 4.02 0.02100
Signal Layer 1 1.20 3.38 0.02984
Laminate Layer 2 3.90 4.02 0.02100
Copper Plane Bottom 1.30 3.20
DC resistance by dimensions:
Rdc_trace_1= 131.53 Rdc_trace_2 = 131.53 milliohms/in 20C
DC resistance by pixel count:
Rdc_trace_1= 131.531 Rdc_trace_2 = 131.531 milliohm/in
C_odd = 4.221 pF/in C_even = 3.968 pF/in
Er_odd = 3.923 Er_even = 3.947
Loss_tan_o = 0.02212 Loss_tan_e = 0.02184
Delay_odd = 167.801 Delay_even = 168.314 ps/in.
Z_diff = 79.501 ohms Z_comm = 21.209 ohms
Simulation pix map 122 pixels high by 800 pixels wide.
293824 bytes allocated for bmp.
INPUT PARAMETERS:
Layer Thick Specifications
Copper Plane Top 1.30 Opening w=0.0 offset=0.0
Laminate Layer 1 4.20 Resin Content 75.0% 3.4-4.9
Signal Layer 1 1.20 4.5-7.0-4.5 Etchback=0.00
Laminate Layer 2 4.20 Resin Content 75.0% 3.4-4.9
Copper Plane Bottom 1.30 Opening w=0.0 offset=0.0
Layer Thick Er Loss Tangent
Copper Plane Top 1.30 3.20
Laminate Layer 1 4.20 3.75 0.02470
Signal Layer 1 1.20 3.38 0.02984
Laminate Layer 2 4.20 3.75 0.02470
Copper Plane Bottom 1.30 3.20
DC resistance by dimensions:
Rdc_trace_1= 125.69 Rdc_trace_2 = 125.69 milliohms/in 20C
DC resistance by pixel count:
Rdc_trace_1= 125.685 Rdc_trace_2 = 125.685 milliohm/in
C_odd = 3.929 pF/in C_even = 3.624 pF/in
Er_odd = 3.694 Er_even = 3.710
Loss_tan_o = 0.02537 Loss_tan_e = 0.02518
Delay_odd = 162.844 Delay_even = 163.195 ps/in.
Z_diff = 82.900 ohms Z_comm = 22.519 ohms
Log file save name:
mdtlc_12100946383.txt
Simulation pix map 118 pixels high by 780 pixels wide.
277144 bytes allocated for bmp.
INPUT PARAMETERS:
Layer Thick Specifications
Copper Plane Top 1.30 Opening w=0.0 offset=0.0
Laminate Layer 1 4.00 Resin Content 45.0% 2.6-5.1
Signal Layer 1 1.20 4.1-7.4-4.1 Etchback=0.00
Laminate Layer 2 4.00 Resin Content 45.0% 2.6-5.1
Copper Plane Bottom 1.30 Opening w=0.0 offset=0.0
Layer Thick Er Loss Tangent
Copper Plane Top 1.30 3.20
Laminate Layer 1 4.00 3.98 0.01140
Signal Layer 1 1.20 2.64 0.01690
Laminate Layer 2 4.00 3.98 0.01140
Copper Plane Bottom 1.30 3.20
DC resistance by dimensions:
Rdc_trace_1= 137.95 Rdc_trace_2 = 137.95 milliohms/in 20C
DC resistance by pixel count:
Rdc_trace_1= 137.947 Rdc_trace_2 = 137.947 milliohm/in
C_odd = 3.910 pF/in C_even = 3.695 pF/in
Er_odd = 3.769 Er_even = 3.817
Loss_tan_o = 0.01202 Loss_tan_e = 0.01189
Delay_odd = 164.490 Delay_even = 165.524 ps/in.
Z_diff = 84.134 ohms Z_comm = 22.396 ohms
Simulation pix map 118 pixels high by 795 pixels wide.
282454 bytes allocated for bmp.
INPUT PARAMETERS:
Layer Thick Specifications
Copper Plane Top 1.30 Opening w=0.0 offset=0.0
Laminate Layer 1 4.00 Resin Content 54.0% 2.6-5.1
Signal Layer 1 1.20 4.4-7.1-4.4 Etchback=0.00
Laminate Layer 2 4.00 Resin Content 54.0% 2.6-5.1
Copper Plane Bottom 1.30 Opening w=0.0 offset=0.0
Layer Thick Er Loss Tangent
Copper Plane Top 1.30 3.20
Laminate Layer 1 4.00 3.76 0.01230
Signal Layer 1 1.20 2.64 0.01690
Laminate Layer 2 4.00 3.76 0.01230
Copper Plane Bottom 1.30 3.20
DC resistance by dimensions:
Rdc_trace_1= 128.54 Rdc_trace_2 = 128.54 milliohms/in 20C
DC resistance by pixel count:
Rdc_trace_1= 128.542 Rdc_trace_2 = 128.542 milliohm/in
C_odd = 3.865 pF/in C_even = 3.623 pF/in
Er_odd = 3.588 Er_even = 3.631
Loss_tan_o = 0.01283 Loss_tan_e = 0.01270
Delay_odd = 160.480 Delay_even = 161.455 ps/in.
Z_diff = 83.041 ohms Z_comm = 22.280 ohms
看完之后，我有一事不明，我总是分不清奇偶，不知道这两者到底如何区分，亲，你能告诉我吗?
我以前也分不清奇偶，后来强行记住了even是偶，搞的后来一看到odd，就要先想even是“偶”，odd只好是“奇”了，很是麻烦！
你这一提醒，我以后可以换个记法了：odd是3个字母，“奇”数个字母；even是4个字母，“偶”数个字母。哈哈
晕， 小编居然转贴到这里来了！
汗！