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LPC2939设计在MCU USB接口技术的应用

时间:01-06 来源:互联网 点击:

hronize PWM and ADC

Quadrature encoder interface that can monitor one external quadrature encoder

32-bit watchdog with timer change protection, running on safe clock

Up to 152 general-purpose I/O pins with programmable pull-up, pull-down, or bus keeper

Vectored Interrupt Controller (VIC) with 16 priority levels

Up to 22 level-sensitive external interrupt pins, including USB, CAN and LIN wake-up features

Configurable clock-out pin for driving external system clocks

Processor wake-up from Power-down via external interrupt pins and CAN or LIN activity

Flexible Reset Generator Unit (RGU) able to control resets of individual modules

Flexible Clock-Generation Unit (CGU) able to control clock frequency of individual modules:

On-chip very low-power ring oscillator; fixed frequency of 0.4 MHz; always on to provide a Safe_Clock source for system monitoring

On-chip crystal oscillator with a recommended operating range from 10 MHz to 25 MHz. PLL input range 10 MHz to 25 MHz.

On-chip PLL allows CPU operation up to a maximum CPU rate of 125 MHz

Generation of up to 11 base clocks

Seven fractional dividers

Second, dedicated CGU with its own PLL generates USB clocks and a configurable clock output

Highly configurable system Power Management Unit (PMU):

clock control of individual modules

allows minimization of system operating power consumption in any configuration

Standard ARM test and debug interface with real-time in-circuit emulator

Boundary-scan test supported

ETM/ETB debug functions with 8 kB of dedicated SRAM also accessible for application code and data storage

Dual power supply:

CPU operating voltage: 1.8 V ? 5 %

I/O operating voltage: 2.7 V to 3.6 V; inputs tolerant up to 5.5 V

208-pin LQFP package

图1.LPC2939方框图

图2.LPC2939自供电设备USB接口方框图


图3.LPC2939总线供电设备USB接口方框图

图4.LPC2939 USB OTG端口配置:USB端口1 OTG双任务设备,USB端口2主机

图5.LPC2939 USB OTG端口配置:USB端口1主机,USB端口2主机

图6.LPC2939 USB OTG端口配置:USB端口2设备,USB端口1主机

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