CAN总线控制器IP核的代码分析

out_regs;

end

end

`ifdef CAN_WISHBONE_IF

// Combining wb_cyc_i and wb_stb_i signals to cs signal. Than synchronizing to clk_i clock domain.

always @ (posedge clk_i or posedge rst)

begin

if (rst)

begin

cs_sync1 = 1'b0;

cs_sync2 = 1'b0;

cs_sync3 = 1'b0;

cs_sync_rst1 = 1'b0;

cs_sync_rst2 = 1'b0;

end

else

begin

cs_sync1 =#Tp wb_cyc_i wb_stb_i (~cs_sync_rst2) cs_can_i;

cs_sync2 =#Tp cs_sync1 (~cs_sync_rst2);

cs_sync3 =#Tp cs_sync2 (~cs_sync_rst2);

cs_sync_rst1 =#Tp cs_ack3;

cs_sync_rst2 =#Tp cs_sync_rst1;

end

end

assign cs = cs_sync2 (~cs_sync3);

always @ (posedge wb_clk_i)

begin

cs_ack1 =#Tp cs_sync3;

cs_ack2 =#Tp cs_ack1;

cs_ack3 =#Tp cs_ack2;

end

// Generating acknowledge signal

always @ (posedge wb_clk_i)

begin

wb_ack_o =#Tp (cs_ack2 (~cs_ack3));

end

assign rst = wb_rst_i;

assign we = wb_we_i;

assign addr = wb_adr_i;

assign data_in = wb_dat_i;

assign wb_dat_o = data_out;

`else

// Latching address

always @ (negedge clk_i or posedge rst)

begin

if (rst)

addr_latched = 8'h0;

else if (ale_i)

addr_latched =#Tp port_0_io;

end

// Generating delayed wr_i and rd_i signals

always @ (posedge clk_i or posedge rst)

begin

if (rst)

begin

wr_i_q = 1'b0;

rd_i_q = 1'b0;

end

else

begin

wr_i_q =#Tp wr_i;

rd_i_q =#Tp rd_i;

end

end

assign cs = ((wr_i (~wr_i_q)) | (rd_i (~rd_i_q))) cs_can_i;

assign rst = rst_i;

assign we = wr_i;

assign addr = addr_latched;

assign data_in = port_0_io;

assign port_0_io = (cs_can_i rd_i)? data_out : 8'hz;

`endif

endmodule