S3C2410中断机制及相关寄存器介绍
有效位为32,INTSUBMSK有效位为11,这两个寄存器各个位与SRCPND和SUBSRCPND分别对应。它们的作用是决定该位相应的中断请求是否被处理。若某位被设置为1,则该位相对应的中断产生后将被忽略(CPU不处理该中断请求),设置为0则对其进行处理。这两个寄存器初始化后的值是0xFFFFFFFF和0x7FF,既默认情况下所有的中断都是被屏蔽的。如表1-6所示。
寄存器 | 地址 | 描述 |
INTMSK | 0X4A000008 | 0 =Interrupt service is available, 1= Interrupt service is masked |
表1-6INTMSK寄存器
(4)PRIORITY寄存器
一个嵌入式系统一般有多个中断请求源。当多个中断源同时请求中断时,就会存在CPU应该优先响应哪个中断请求源的问题,如果处理不当将会引起混乱,导致系统不能正常工作。通常解决这个问题的方法是根据中断源事件的轻重缓急规定中断源的优先级,CPU优先响应中断优先级高的中断请求。
S3C2410的优先级判断分为两级。如图1-3所示,SRCPND寄存器对应的32个中断源总共被分为6个组,每个组由一个ARBITER(0~5)寄存器对其进行管理。中断必须先由所属组的ARBITER(0~5)进行第一次优先级判断(第一级判断)后再发往ARBITER6进行最终的判断(第二级判断)。ARBITER(0~5)这六个组的优先级已经固定,由ARBITER0控制的组优先级最高,其次是ARBITER1, ARBITER2, ARBITER3, ARBITER4, ARBITER5。但是每个组中的各个中断的优先级是可以控制的,我们只需要设置PRIORITY的相应位。
图1-3 Priority Generating Block
INTERRUPT PRIORITY
Each arbiter can handle six interrupt requests based on the one bit arbiter mode control (ARB_MODE) and two bits of selection control signals (ARB_SEL) as follows:
— If ARB_SEL bits are 00b, the priority order is REQ0, REQ1, REQ2, REQ3, REQ4, and REQ5.
— If ARB_SEL bits are 01b, the priority order is REQ0, REQ2, REQ3, REQ4, REQ1, and REQ5.
— If ARB_SEL bits are 10b, the priority order is REQ0, REQ3, REQ4, REQ1, REQ2, and REQ5.
— If ARB_SEL bits are 11b, the priority order is REQ0, REQ4, REQ1, REQ2, REQ3, and REQ5.
Note that REQ0 of an arbiter always has the highest priority, and REQ5 has the lowest one. In addition, by changing the ARB_SEL bits, we can rotate the priority of REQ1 to REQ4.
Here,if ARB_MODE bit is set to 0, ARB_SEL bits are not automatically changed, making the arbiter to operate in the fixed priority mode (note that even in this mode, we can reconfigure the priority by manually changing the ARB_SEL bits). On the other hand, if ARB_MODE bit is 1, ARB_SEL bits are changed in rotation fashion, e.g., if REQ1 is serviced, ARB_SEL bits are changed to 01b automatically so as to put REQ1 into the lowest priority. The detailed rules of ARB_SEL change are as follows:
— If REQ0 or REQ5 is serviced, ARB_SEL bits are not changed at all.
— If REQ1 is serviced, ARB_SEL bits are changed to 01b.
— If REQ2 is serviced, ARB_SEL bits are changed to 10b.
— If REQ3 is serviced, ARB_SEL bits are changed to 11b.
— If REQ4 is serviced, ARB_SEL bits are changed to 00b.
PRIORITY | BIT | 描述 |
ARB_SEL6 | [20:19] | Arbiter 6 group priority order set 00:REQ 0-1-2-3-4-5,01:REQ 0-2-3-4-1-5 10:REQ 0-3-4-1-2-5,11:REQ 0-4-1-2-3-5 |
ARB_SEL5 | [18:17] | Arbiter 5 group priority order set 00:REQ 0-1-2-3-4-5,01:REQ 0-2-3-4-1-5 10:REQ 0-3-4-1-2-5,11:REQ 0-4-1-2-3-5 |
ARB_SEL4 | [16:15] | Arbiter 4 group priority order set 00:REQ 0-1-2-3-4-5,01:REQ 0-2-3-4-1-5 10:REQ 0-3-4-1-2-5,11:REQ 0-4-1-2-3-5 |
ARB_SEL3 | [14:13] | Arbiter 3 group priority order set 00:REQ 0-1-2-3-4-5,01:REQ 0-2-3-4-1-5 10:REQ 0-3-4-1-2-5,11:REQ 0-4-1-2-3-5 |
ARB_SEL2 | [12:11] | Arbiter 2 group priority order set 00:REQ 0-1-2-3-4-5,01:REQ 0-2-3-4-1-5 10:REQ 0-3-4-1-2-5,11:REQ 0-4-1-2-3-5 |
ARB_SEL1 | [10:9] | Arbiter 1 group priority order set 00:REQ 0-1-2-3-4-5,01:REQ 0-2-3-4-1-5 10:REQ 0-3-4-1-2-5,11:REQ 0-4-1-2-3-5 |
ARB_SEL0 | [8:7] | Arbiter 0 group priority order set 00:REQ 1-2-3-4,01:REQ 2-3-4-1 1 |
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