avr的外部中断

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http://www.ouravr.com/bbs/bbs_content.jsp?bbs_sn=691118&bbs_page_no=1&bbs_id=1000

http://www.c51bbs.com/c51bbs/topic1/c51bbs17322.htm

但最终呢，真正的原因是在AVR-GCC的帮助文档avr-libc本来就有的，FAQ24，Why are (many) interrupt flags cleared by writing a logical 1?当然，你的E文要好地。

参见如下说明：

Why are (many) interrupt flags cleared by writing a logical 1?

Usually, each interrupt has its own interrupt flag bit in some control register, indicating the specified interrupt condition has been met by representing a logical1 inthe respective bit position. When working with interrupt handlers, this interrupt flag bit usually gets cleared automatically in the course of processing the interrupt, sometimes by just calling the handler at all, sometimes (e. g. for the U[S]ART) by reading a particular hardware register that will normally happen anyway when processing the interrupt.

From the hardwares point of view, an interrupt is asserted as long as the respective bit is set, while global interrupts are enabled. Thus, it is essential to have the bit cleared before interrupts get re-enabled again (which usually happens when returning from an interrupt handler).

Only few subsystems require an explicit action to clear the interrupt request when using interrupt handlers. (The notable exception is the TWI interface, where clearing the interrupt indicates to proceed with the TWI bus hardware handshake, so its never done automatically.)

However, if no normal interrupt handlers are to be used, or in order to make extra sure any pending interrupt gets cleared before re-activating global interrupts (e. g. an external edge-triggered one), it can be necessary to explicitly clear the respective hardware interrupt bit by software. This is usually done by writing a logical 1 into this bit position. This seems to be illogical at first, the bit position already carries a logical 1 when reading it,so why does writing a logical 1 to it clear the interrupt bit?

The solution is simple:writing a logical 1 to it requires only a single OUT instruction, and it is clear that only this single interrupt request bit will be cleared. There is no need to perform a read-modify-write cycle (like, an SBI instruction), since all bits in these control registers are interrupt bits, and writing a logical 0 to the remaining bits (as it is done by the simple OUT instruction) will not alter them, so there is no risk of any race condition that might accidentally clear another interrupt request bit. So instead of writing

TIFR |= _BV(TOV0); /* wrong! */

simply use

TIFR = _BV(TOV0);

2．只要使能了中断，即使引脚INT7:0配置为输出，只要电平发生了合适的变化，中断也会触发.这句怎么理解？答：也就是说，你打开了中断int0和int1，同时这两个管脚定义为输出，然后，你使用软件设置这两个管脚的输出电平，当满足中断条件时，中断就发生了。这不就是软件中断吗？

3．在配置了外部中断控制寄存器、屏蔽寄存器、标志寄存器后，是否还需要设置IO口为输入端口呢？答：是的，不过IO口上电时就默认是输入了，可以不写这条指令。补充，设置成输出也照样产生中断。它用PINx读。