Launch-off-shift实时测试

Implement PLL Clock Switching for At-Speed Test, Chip Design Magazine, February/March 2006. www.chipdesignmag.com/display.php?articleId=376issueId=15.
5. Beck, M., et al., “Logic Design for On-Chip Test Clock Generation—Implementation Details and Impact on Delay Test Quality,” Design Automation and Test in Europe 2005. date.eda-online.co.uk/proceedings/papers/2005/year.htm.
6. Haioun, E., et al., “At-Speed Scan Transition and Path Delay Testing Using On-Chip PLL for High Frequency Device and Low Frequency Tester,” Euro DesignCon 2005, www.iec.org/events/2005/euro_designcon.
7. “Use of Registered/Pipelined Scan Enable for At-Speed Testing in FastScan/TestKompress,” Mentor Graphics, April 2006.
8. Rearick, J., “Too Much Delay Fault Coverage Is a Bad Thing.” Proceedings of the International Test Conference 2001, IEEE Computer Society Press.
9. Vorisek, V., et al., “Improved Handling of False and Multicycle Paths in ATPG,” Proceedings of the 24th IEEE VLSI Test Symposium (VTS 06), IEEE Computer Society Press.
10. Linn, X., et al., “Timing-Aware ATPG: A Novel Test Generation Method for High-Quality At-speed Test,” ATS 2006, the Fifteenth Asian Test Symposium, ats06.cs.ehime-u.ac.jp.
11. “ITC: LogicVision debuts ScanBurst, teams with Mentor,” Test Measurement World, October 26, 2006. www.tmworld.com.