基于网络编码的多信源组播通信系统，包括源代码，原理图等(四)

val_router_multiplier_1<= 0; //clear valid signal

//confirm the first random number is generated successfully

//before enable to generate the second.

if (ctrl_temp1 == 8'hff) begin

if (!rand_num_val) begin

rand_num_en <= 0;

router_status <= SEND_BOTH_2;

end

end else begin

if (!rdy_router_multiplier_2) begin

val_router_multiplier_2 <= 0;

router_status <= SEND_BOTH_2;

end

else begin

data_router_multiplier_2 <= data_temp2;

val_router_multiplier_2 <= 1;

if (ctrl_temp2 == 8'hff) begin

first_dword_2 <= 1;

rand_num_en <= 1;

end

else begin

first_dword_2 <= 0;

rand_num_en <= 0;

end

if (((ctrl_temp1 == 8'hf0) && (& (ctrl_temp2))) || ((ctrl_temp2 == 8'hf0) && (& (ctrl_temp1)))) begin

router_status <= JUDGE;

end

else begin

rd_en_payloadfifo_router_1 <= 1;

rd_en_payloadfifo_router_2 <= 1;

counter_getdata <= 0;

router_status <= GET_BOTH;

end

end

end

end //state SEND_BOTH_2 ends

endcase

end

end

endmodule

附2：解码路由器核心代码之一：解码控制模块：decode_control_sm. v

///////////////////////////////////////////////////////////////////////////////

// vim:set shiftwidth=3 softtabstop=3 expandtab:

// Copyright(c) 2009, All rights reserved.

// Advanced Network technology Lab, Shenzhen graduated school of PKU

// Module: decode_control_sm.v

// Project: NF2.1

// Time and Author: 2009-12-15 zhang ming long

// Description: According to the pkts' source and generation sequence number,

// this module goes round-robin strategy to control the module decoder

// to decode the pkts stored in DRAMS.

///////////////////////////////////////////////////////////////////////////////

`define DLY #1

`timescale 1ns/1ps

module decode_control_sm

#(parameter SRC_WIDTH = 4,

parameter GEN_WIDTH = 8,

parameter REG_GRP_WIDTH = 12,

parameter SRC_GEN_SEQ_WIDTH = 24,

parameter DRAM_NUMS = 3,

parameter CAM_NUMS = 3,

parameter DRAM_NUMS_WIDTH = log2(DRAM_NUMS),

parameter CAM_NUMS_WIDTH = log2(CAM_NUMS),

parameter DRAM_BLOCK_WIDTH = 8,

parameter CAM_ADDR_WIDTH = 8,

parameter CMP_DATA_MASK = 12'hfff

)

(// --- cam interface

output [SRC_GEN_SEQ_WIDTH-1:0] cmp_data_0,

output reg [SRC_GEN_SEQ_WIDTH-1:0] cmp_data_mask_0,

input [CAM_ADDR_WIDTH-1:0] match_addr_0,

input match_0,

output [SRC_GEN_SEQ_WIDTH-1:0]

output [SRC_GEN_SEQ_WIDTH-1:0] cmp_data_1,

output reg [SRC_GEN_SEQ_WIDTH-1:0] cmp_data_mask_1,

input [CAM_ADDR_WIDTH-1:0] match_addr_1,

input match_1,

output [SRC_GEN_SEQ_WIDTH-1:0] cmp_data_2,

output reg [SRC_GEN_SEQ_WIDTH-1:0] cmp_data_mask_2,

input [CAM_ADDR_WIDTH-1:0] match_addr_2,

input match_2,

// ---DRAM control interface

output reg [DRAM_NUMS_WIDTH-1:0] port_num_rd,

output reg [DRAM_BLOCK_WIDTH-1:0] block_num_rd,

output reg addr_vld,

input rd_idle,

// ---input_arbiter interface

input cam_vld,

// ---decoder interface

output reg pkt_vld,

output reg [REG_GRP_WIDTH-1:0] pkt_dcoding,

output reg pkt_not_find,

output reg has_other_factor,

input [REG_GRP_WIDTH-1:0] pkt_need_src_gen,

input need_pkt_vld,

input decod_com,

// ---decoded reg grp interface

output reg rd_dcod_reg_req_1,

output [REG_GRP_WIDTH-1:0] rd_dcod_src_gen_1,

input req_ack_vld_1,

input alredy_decod_1,

// --- Misc

input rst_n,

input clk

); function integer log2;

input integer number;

begin

log2=0;

while(2**log2

log2=log2+1;

end

end

endfunction // log2

// ------------ Internal Params --------

parameter NUM_STATES = 4;

parameter IDLE = 4'b0;

parameter GET_SRC_GEN_NUM = 4'b0001;

parameter LOOK_UP_CAM = 4'b0010;

parameter GET_CMP_RESLT_FIRST = 4'b0011;

parameter GET_CMP_RESLT_SEC = 4'b0100;

parameter RD_DRAM_MAIN_STEP = 4'b0101;

parameter LUP_DCOD_FACTOR1_FIRST = 4'b0110;

parameter LUP_DCOD_FACTOR1_SEC = 4'b0111;

parameter GET_FACTOR1_RESLT = 4'b1000;

parameter RD_DRAM_MINOR_STEP = 4'b1001;

parameter LUP_DCOD_FACTOR2 = 4'b1011;

// ----