FIFO 同步、异步以及Verilog代码实现

以下代码在modelsim中验证过。
module fifo_cell (sys_clk, sys_rst_n, read_fifo, write_fifo, fifo_input_data,                        next_cell_data, next_cell_full, last_cell_full, cell_data_out, cell_full);                        parameter WIDTH =8;                        parameter D = 2;                        input sys_clk;                        input sys_rst_n;                        input read_fifo, write_fifo;                        input [WIDTH-1:0] fifo_input_data;                        input [WIDTH-1:0] next_cell_data;                        input next_cell_full, last_cell_full;                        output [WIDTH-1:0] cell_data_out;                        output cell_full;                        reg [WIDTH-1:0] cell_data_reg_array;                        reg [WIDTH-1:0] cell_data_ld;                        reg cell_data_ld_en;                        reg cell_full;                        reg cell_full_next;                        assign cell_data_out=cell_data_reg_array;                        always @(posedge sys_clk or negedge sys_rst_n)                           if (!sys_rst_n)                              cell_full <= #D 0;                           else if (read_fifo || write_fifo)                              cell_full <= #D cell_full_next;                        always @(write_fifo or read_fifo or next_cell_full or last_cell_full or cell_full)                           casex ({read_fifo, write_fifo})                               2'b00: cell_full_next = cell_full;                               2'b01: cell_full_next = next_cell_full;                               2'b10: cell_full_next = last_cell_full;                               2'b11: cell_full_next = cell_full;                           endcase                         always @(posedge sys_clk or negedge sys_rst_n)                              if (!sys_rst_n)                                 cell_data_reg_array [WIDTH-1:0] <= #D 0;                              else if (cell_data_ld_en)                                 cell_data_reg_array [WIDTH-1:0] <= #D cell_data_ld [WIDTH-1:0];                         always @(write_fifo or read_fifo or cell_full or last_cell_full)                                 casex ({write_fifo,read_fifo,cell_full,last_cell_full})                                  4'bx1_xx: cell_data_ld_en = 1'b1;                                  4'b10_01: cell_data_ld_en = 1'b1;                                  default: cell_data_ld_en =1'b0;                              endcase                         always @(write_fifo or read_fifo or next_cell_full or cell_full or last_cell_full or fifo_input_data or next_cell_data)                              casex ({write_fifo, read_fifo, next_cell_full, cell_full, last_cell_full})                                 5'b10_x01: cell_data_ld[WIDTH-1:0] = fifo_input_data[WIDTH-1:0];                                 5'b11_01x: cell_data_ld[WIDTH-1:0] = fifo_input_data[WIDTH-1:0];                                 default: cell_data_ld[WIDTH-1:0] = next_cell_data[WIDTH-1:0];                              endcaseendmodule
 
module fifo_4cell(sys_clk, sys_rst_n, fifo_input_data, write_fifo, fifo_out_data,                  read_fifo, full_cell0, full_cell1, full_cell2, full_cell3);                  parameter WIDTH = 8;                  parameter D = 2;                  input sys_clk;                  input sys_rst_n;                  input [WIDTH-1:0] fifo_input_data;                  output [WIDTH-1:0] fifo_out_data;                  input read_fifo, write_fifo;                  output full_cell0, full_cell1, full_cell2, full_cell3;                  wire [WIDTH-1:0] dara_out_cell0, data_out_cell1, data_out_cell2,                                   data_out_cell3, data_out_cell4;                  wire full_cell4;                  fifo_cell #(WIDTH,D) cell0                  ( .sys_clk (sys_clk),                    .sys_rst_n (sys_rst_n),                    .fifo_input_data (fifo_input_data[WIDTH-1:0]),                    .write_fifo (write_fifo),                    .next_cell_data (data_out_cell1[WIDTH-1:0]),                    .next_cell_full (full_cell1),                    .last_cell_full (1'b1),                    .cell_data_out (fifo_out_data [WIDTH-1:0]),                    .read_fifo (read_fifo),                    .cell_full (full_cell0)                   );
                  fifo_cell #(WIDTH,D) cell1                  ( .sys_clk (sys_clk),                    .sys_rst_n (sys_rst_n),                    .fifo_input_data (fifo_input_data[WIDTH-1:0]),                    .write_fifo (write_fifo),                    .next_cell_data (data_out_cell2[WIDTH-1:0]),                    .next_cell_full (full_cell2),                    .last_cell_full (full_cell0),                    .cell_data_out (data_out_cell1[WIDTH-1:0]),                    .read_fifo (read_fifo),                    .cell_full (full_cell1)                   );                                    fifo_cell #(WIDTH,D) cell2                  ( .sys_clk (sys_clk),                    .sys_rst_n (sys_rst_n),                    .fifo_input_data (fifo_input_data[WIDTH-1:0]),                    .write_fifo (write_fifo),                    .next_cell_data (data_out_cell3[WIDTH-1:0]),                    .next_cell_full (full_cell3),                    .last_cell_full (full_cell1),                    .cell_data_out (data_out_cell2[WIDTH-1:0]),                    .read_fifo (read_fifo),                    .cell_full (full_cell2)                   );                  
                  fifo_cell #(WIDTH,D) cell3                  ( .sys_clk (sys_clk),                    .sys_rst_n (sys_rst_n),                    .fifo_input_data (fifo_input_data[WIDTH-1:0]),                    .write_fifo (write_fifo),                    .next_cell_data (data_out_cell4[WIDTH-1:0]),                    .next_cell_full (full_cell4),                    .last_cell_full (full_cell2),                    .cell_data_out (data_out_cell3[WIDTH-1:0]),                    .read_fifo (read_fifo),                    .cell_full (full_cell3)                   );                        assign data_out_cell4[WIDTH-1:0] = {WIDTH{1'B0}};                   assign full_cell4 = 1'b0;endmodule                              
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异步FIFO的Verilog代码 之一