基于Xilinx FPGA的通用信号采集器

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254源代码1.Verilog源代码，dataCollect.vmodule dataCollect(sysclk, rst, adda, addb, addc, start, oe,         datain, led_sel, led_seg);    input sysclk, rst;    input wire [7:0] datain;    output reg adda, addb, addc, start, oe;    output reg[3:0] led_sel;    output reg[7:0] led_seg;     reg [3:0] counter1;    reg [7:0] readdata;     reg [9:0] counter2;    reg [15:0] sum;    reg [7:0] averdata;     reg [7:0] temp;    reg [3:0] dataout1, dataout2, dataout3;     reg [3:0] counter3;     parameter ZERO = 8'b11111100,ONE = 8'b01100000, TWO = 8'b11011010;    parameter THREE = 8'b11110010, FOUR =8'b01100110;    parameter FIVE = 8'b10110110, SIX = 8'b10111110, SEVEN =8'b11100000;    parameter EIGHT = 8'b11111110, NINE = 8'b11110110, BLANK = 8'b00000000;      always @(posedge sysclk or negedge rst)    begin        if (!rst)        begin            adda = 0;            addb = 0;            addc = 0;             oe = 1;             counter1 = 0;        end        else        begin            counter1 = counter1 + 1;            case (counter1)                3 : start = 0;                4 : start = 1;                5 : start = 0;                10 : readdata = datain;                15 : counter1 = 0;                default : counter1 = counter1;            endcase        end    end     always @(posedge sysclk or negedge rst)    begin        if (!rst)        begin            counter2 = 0;            sum = 0;            averdata = 0;        end        else        begin            counter2 = counter2 + 1;            if ((counter2%16) == 0)                sum = sum + readdata;            else if (counter2 > 512)            begin                averdata = sum / 32;                sum = 0;                counter2 = 0;            end        end    end      always @(averdata)    begin        temp = averdata;        if (temp > 199)            dataout3 = 2;        else if (temp > 99)            dataout3 = 1;        else            dataout3 = 0;                temp = temp - dataout3 * 100;        if (temp > 89)            dataout2 = 9;        else if (temp > 79)            dataout2 = 8;        else if (temp > 69)            dataout2 = 7;        else if (temp > 59)            dataout2 = 6;        else if (temp > 49)            dataout2 = 5;        else if (temp > 39)            dataout2 = 4;        else if (temp > 29)            dataout2 = 3;        else if (temp > 19)            dataout2 = 2;        else if (temp > 9)            dataout2 = 1;        else            dataout2 = 0;         temp = temp - dataout2 * 10;        dataout1 = temp;         if ((dataout3==0) && (dataout2==0))        begin            dataout3 = 10;            da