MSP430F522x和MSP430F521x设计注意事项

nd XT2IN and XT2OUT (XT2) pins are multiplexed with the general-purpose I/O pins that reside on the DVCC supply domain. When the XT1 and XT2 oscillators are configured in crystal bypass mode, the XIN and XT2IN pins, respectively, can accept external clock input signals, and the XOUT and XT2OUT pins, respectively, can be configured as general- purpose I/O pins that are supplied by DVCC.

7 Bootstrap Loader (BSL)

The BSL enables users to program the flash memory or RAM using a serial interface. The F522x and F521x devices come with UART as the default BSL serial interface. Access to the device memory via the BSL is protected by a user-defined password. Because the F522x and F521x devices have split I/O power domains, it is possible to interface with the BSL from either the DVCC or DVIO supply domains.

Table 1 shows the various device pins used for DVCC and DVIO supplied BSL interfaces. For more details, see the BSL description in F522x and F521x data sheet [1].

Table 1. DVCC and DVIO Supplied BSL Interfaces

BSL Function DVCC Supplied BSL Interface DVIO Supplied BSL Interface

External Reset RSTDVCC/SBWTDIO RST/NMI

Enable BSL TEST/SBWTCK BSLEN

Data Transmit P1.1 (Timer_A UART) P3.3/UCA0TXD (USCI_A0 UART)

Data Receive P1.2 (Timer_A UART) P3.4/UCA0RXD (USCI_A0 UART)

Device Power Supply DVCC, AVCC DVCC, AVCC

I/O Power Supply DVIO DVIO

Ground Supply DVSS DVSS

For single-supply systems (DVIO connected to DVCC) in which the DVCC supplied BSL interface is used, specific BSL entry and exit sequences are generated using the RSTDVCC/SBWTDIO and TEST/SBWTCK pins. These are the standard RESET and TEST based BSL entry and exit sequences that apply to all non- USB F5xx and F6xx devices, and the standard TI supplied BSL tools can be used to access the device.

For split-supply I/O systems in which the DVIO supplied BSL interface is used, specific BSL entry and exit sequences should be generated using the RST/NMI and BSLEN pins, and these sequences apply only to the DVIO supplied BSL interface.

4 Designing With MSP430F522x and MSP430F521x Devices SLAA558–November 2012 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated

BSLEN

RST

BSLEN

RST

www.ti.com Bootstrap Loader (BSL)

7.1 BSL Entry Sequence for DVIO Supplied BSL Interface

BSLEN is the BSL enable pin with internal pull down resistor enabled and the BSL entry sequence involves toggling the RST/NMI pin (high-low-high transition) with the BSLEN pin pulled high (see Figure 3).

A The minimum timing for this sequence must be within the limits specified for the corresponding pins in the data sheet.

Figure 3. BSL Entry Sequence for DVIO Supplied BSL Interface

Note 2:The BSLEN pin need not be pulled high during the entire period when the device is in BSL mode. However, the BSLEN pin is required to be pulled high for a minimum period of time after the RST/NMI pin goes low-high for proper BSL invoke. See the F522x and F521x data sheet [1] for the timing specifications.

7.2 BSL Exit Sequence for DVIO Supplied BSL Interface

The BSL exit sequence of the DVIO supplied BSL interface involves toggling the RST/NMI pin (high-low- high transition) with the BSLEN pin pulled low (see Figure 4).

A The minimum timing for this sequence must be within the limits specified for the corresponding pins in the data sheet.

Figure 4. BSL Exit Sequence for DVIO Supplied BSL Interface

For complete description of the BSL entry and exit sequences (for both DVCC and DVIO supplied BSL interfaces), features and its implementation, see the MSP430 Programming Via the Bootstrap