MSP430F522x和MSP430F521x设计注意事项

For split-supply I/O systems, it is required that the VIO ≥ VCC during the ramp up phase of VIO and VCC. During VCC and VIO power down, it is required that VIO ≥ VCC during the ramp down phase of VIO and VCC. Figure 2 is an excerpt from the data sheet.

NOTE: The device supports continuous operation with VCC = VSS while VIO is fully within its specification. During this time, the general-purpose I/Os that reside on the VIO supply domain are configured as inputs and pulled down to VSS through their internal pulldown resistors. RST/NMI is high impedance. BSLEN is configured as an input and is pulled down to VSS through its internal pulldown resistor. When VCC reaches above the BOR threshold, the general-purpose I/Os become high-impedance inputs (no pullup or pulldown enabled), RST/NMI becomes an input pulled up to VIO through its internal pullup resistor, and BSLEN remains pulled down to VSS through its internal pulldown resistor. Figure 2. VCC and VIO Power Sequencing

5 Reset and NMI Pin Functionality

On the F522x and F521x devices, there are two reset pins: • RSTDVCC/SBWTDIO: resides on the DVCC supply domain • RST/NMI: resides on the DVIO supply domain The device can be held in reset by asserting a low on either of the two reset pins. However, the NMI pin functionality is available only on the RST/NMI pin and is not multiplexed with the RSTDVCC pin.

The RSTDVCC pin has an internal pullup that is always enabled and is not configurable. The RST/NMI pin has configurable internal pullup and pulldown resistors available. By default, the internal pullup resistor on the RST/NMI pin is enabled. The SYSRSTUP and SYSRSTRE bits in the reset pin control register (SFRRPCR) are used to select either the internal pullup or pulldown and to enable them, respectively.

If the RST/NMI pin is unused, select and enable the internal pullup resistor, or connect an external pullup resistor (47 kΩ recommended) to the pin.

NOTE: Because all of the 4-wire JTAG pins (on Port J) reside on the DVCC supply domain, use the RSTDVCC pin which also resides on the DVCC supply domain for the JTAG interface and not the DVIO supplied RST/NMI pin. For more details, see the "JTAG Pin Requirements and Functions" table in the device data sheet [1].

3SLAA558–November 2012 Designing With MSP430F522x and MSP430F521x Devices Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated

XT1 and XT2 Oscillators in Bypass Mode www.ti.com.

6 XT1 and XT2 Oscillators in Bypass Mode

The F522x and F521x devices have two on-chip crystal oscillators: • XT1: low-frequency crystal oscillator XT2: high-frequency crystal oscillator Both XT1 and XT2 oscillators can be operated in crystal bypass mode, in which external clock signals are input to the XIN and XT2IN pins, respectively, and the oscillators associated with XT1 and XT2, respectively, are powered down. By default, the XIN and XT2IN pins reside on the DVCC supply domain and require the external clock signal to meet the data sheet specified input specifications for I/Os in DVCC domain.

Additionally, the F522x and F521x devices support XT1 and XT2 bypass operation with external clock inputs that reside on the DVIO supply domain. Setting the XT1BYPASSLV and XT2BYPASSLV bits in the UCSCTL9 register enables the XT1 and XT2 bypass operations, respectively, with external clock signals that swing from 0 V to DVIO.

In both the cases, the external clock input frequency must meet the data sheet parameters for the chosen mode.

On the F522x and F521x devices, the XIN and XOUT (XT1) a