求解用PADS Logic 生成的网络表的问题
时间：10-02
整理：3721RD
点击：
padsnet.err——记事本
PCB Net List Errors Report - DOTLED1.sch - Wed Nov 09 19:45:31 2011
--------------------------------------------------------------------
Design to Library Part Consistency Check
----------------------------------------
No Library consistency checking errors.
Single/Zero Pin Net Warnings
----------------------------
No single or zero pin nets.
Schematic Connectivity Errors
-----------------------------
Dangling Connections without a Net Name
H8
Sheet 1 X5010 Y11270
Dangling Connections with a Net Name
H10
Sheet 1 X4270 Y9790
请好心人解释上面是那出现问题了。
PCB Net List Errors Report - DOTLED1.sch - Wed Nov 09 19:45:31 2011
--------------------------------------------------------------------
Design to Library Part Consistency Check
----------------------------------------
No Library consistency checking errors.
Single/Zero Pin Net Warnings
----------------------------
No single or zero pin nets.
Schematic Connectivity Errors
-----------------------------
Dangling Connections without a Net Name
H8
Sheet 1 X5010 Y11270
Dangling Connections with a Net Name
H10
Sheet 1 X4270 Y9790
请好心人解释上面是那出现问题了。
X5010 Y112709
X4270 Y9790
查看一下这两个坐标值的地方,存在dangling connect
这两个网点刚好互相连接错误，我以前也遇到过，检查封装和原理图，建议用ORCAD画原理图导网表，logic画元件封装费力。
谢谢大侠，问题已解~
小编的问题是怎么解决的?我也遇到了,说说啊