Problem with negative gain in a wide band LNA design

I am designing WB lna fr freq rand 3.1 Gz to 10 ghz, m using ads fr simulation of schematic......i am getting proper frequecy response for S21 plot bt the gain is negative can ny1 tell wat is the problem..............immediate help is appreciated........
also can ny1 tell me hw to draw layout using ads

Well...meny things could be wrong.

I think you need to supply some extra info?

hey here is the paper i am implementing..........kindly suggest me if there is any mistake in the design procedure

sum1 plzz help.........i require it urgently
@tyassin............plz let me knw wat more information u require

Hi

Sure your can upload the schematic.

Well in this paper LNA is designed by CMOS process.
you should mention first that you are using CMOS process.

you need to upload your results such as NF,Gain S11 etc & schematic.
otherwise no one will be able to comment.

@tyassin, Abhishekabs.......i am attaching the schematic, s-parameters and noise figure graph with this post......plzz let me knw wat the changes to be made to get proper s-aprametes and noise figure

check your connections properly.
I think C3 is not connected properly.
Also I have not done LNA using CMOS but your input side looks strange to me.

Added after 25 minutes:

It looks like C3 is not connected.
I dont have ADS access now so cant check your file.

Hi

Can you also send your design kit?

yup here is the design kit

Hi

I have look at it briefly. I am able to get som gain around 7.5 dB over the complete band. However return loss is nowhere near the paper.

I am to not really a CMOS expert. I have changed the Vbias to obtain a positive gain.

thts great dude atleast u r getting positive gain......i ws trying tht fr last afew days................can u please send me the schematic file.......or mail on ganesh634@gmail.com

Hi

Here is the file.

Otherwise it look OK. Although you have to pay attention that some og the components are a series combination of external and internal transistor components.
Maybee the transistor models are not the same? but CMOS is not my strong point.

Hope it can help

kk i will chk it out and let u knw..........nyways thnxs fr ur valuable help

Hi Tyassin,
I got gain of around 12.5 db over the intrested frequency range......i increased the value of resistor in the o/p stage bt the return loss is still of concern....

Added after 1 minutes:

can nyone plz tell me hw to measure iip3 for the wideband lna using ads

Hi

Check out this document.

hey Tyassin that document was really of great help................thnxs a lot................... please help me regarding how to draw layout of the above ckt using ADS....