asitic *.tek

hi, everyone.

I'm new with ASITIC. In the example of the technology file for ASITIC, there is a metal0 layer which is in the epi layer and this layer is used to ground the substrate.

In my case, the process which I use dose not include the epi layer, but I still need the metal0 layer to ground the surface of my substrate, which layers i should put this metal layer in?

Is the metal0 layer equivalent to the poly layer in the process?

Thanks!

sorry that I don't write you for help, but I've read that you are using asitic
how did you execute asitic?
in what linux or what command do you use in cygwin bash shell


http://rfic.eecs.berkeley.edu/~nikne...26-02/faq.html

Added after 3 minutes:

and for your question i′ve foud this I hope be helpfull

Let's use a generic CMOS process as an example. Below is the technology file for such a CMOS process. The cross-section of the various substrate layers in shown in the figure below. The technology is divided into sub-sections. The first sub-section begins with the <chip> statement. The first two lines in the chip section define the chip x and y dimensions. For best results use the smallest area that you think you will need. Below we define a chip of dimension .5 mm .5 mm. There is a direct relation between the chip size and the FFT sizes appearing on the next two lines. The smallest dimension you can use in the x direction in substrate simulation, for instance, is chipx/fftx. In the example shown below the minimum dimension is 2 m. This will be okay in most cases. This is why I recommend using the smallest chip dimension that you can get away with. Generally, the larger the FFT size, the more memory required by the simulator. Again, use the smallest FFT size that gives you sufficient accuracy. You may find that a 128x128 FFT is good enough. You will save a lot of memory by using the smallest FFT size possible. I will go into more detail about this later. The TechFile is the name of the technology file that you choose, whatever the filename is. The TechPath is where you will place certain binary data files (see Running Gendata).



<chip>

chipx = 512 ; dimensions of the chip in x direction in microns
chipy = 512 ; dimensions of the chip in y direction
fftx = 256 ; x-fft size (must be a power of 2)
ffty = 256 ; y-fft size
TechFile = phil.tek ; the name of this file
TechPath = /home/niknejad/tekf ; the pathname of the data files
freq = .1

<layer> 0 ; Bulk Substrate

rho = .1 ; Resistivity: ohm-cm
t = 400 ; Thickness: microns
eps = 11.9 ; Permitivity: relative

Added after 1 minutes:

<layer> 1 ; Epi Layer

rho = 15 ; ohm-cm
t = 1 ; microns
eps = 11.9 ; relative

<layer> 2 ; Oxide Layer
rho = 1e10 ; ohm-cm
t = 50 ; microns
eps = 4 ; relative

<metal> 0 ; Substrate Contact Layer
layer = 1 ; Epi Layer
rsh = 30 ; Sheet Resistance Milli-Ohms/Square
t = 0.1 ; Metal Thickness (microns)
d = .5 ; Distance from bottom of layer (microns)
name = msub ; name used in ASITIC
color = yellow ; color in ASITIC

<metal> 1
layer = 2
rsh = 50
t = 1
d = 1.62
name = m1
color = red

<metal> 2

layer = 2
rsh = 32
t = 1.3
d = 2.74

Added after 1 minutes:

SUBSTRATE CONTACT LAYER........

Added after 12 minutes:

ACORDING with tanner metal 0 doesnt exist,could be poly 1 or poly 2 acording with the hierarchy in L-edit