IBM45nm (SOI ) technology Gate resistance problem

I am using IBM45nm (SOI) technology provided by MOSIS for designing RF circuits. I used cadence 6.1 to carry out some simulations. When I do typical DC simulation and print the oprating points I do not see the value for gate resistance . Why is this happning? is there no gate resistance in SOI technology? (I checked the BSIMSOI manual and they do model gate resistance and ther RF parameters) I bit confused please help.

Thanks

Gate resistance exists for SOI. The reasoning I could see is i) your model somehow is missing gate resistance values ii) your design or properties are somehow modifying/modified the component property for the library you have created.