x64 frequency multiplier
I need to translate an 80 - 120 Mhz PLL output to the 5120 - 7600 Mhz range. The source has very good phase noise. I consider to use a series of Frequency doublers from Minicircuits. Any other suggestions?
With 6 doublers, you'll also need 6 bandpass filters (some or all of which will be custom) which will make this large and expensive. And if they're passive doublers you'll need 6 amplifiers.
It may be cheaper to split the reference from your current PLL and use that with a PLL/VCO that covers 5-7 GHz. You'll still be phase locked to your reference, get a cleaner signal, and less board space than 6 doublers and 6 BPF.
Frequency doublers are noisy and harmonic generating circuits.
Instead, use Double Balanced Mixer in a single stage.
All you need is a super low noise high K VCO with a /64 prescaler. right...
not easy.
tradeoff between Kvco and Qvco or phase noise
tradeoff with large power consumption and spurious tones
high tuning ratio
Suggest.. ILFD design with /64 prescaler using LC tuned VCO with switch cap range select.
But I am not sure... Mini Circuits are good but I doubt they have a solution in that total range unless special design.
For example assuming your 100 MHz PLL output has a Phase Noise of -130dBc/Hz @ 100kHz offset, and you need a x64 multiplier chain to go to 6400 MHz.
At 6400 MHz the Phase Noise of the signal it will degrade with 20*LOG(64) = 36.1dB, which means: -130dBc/Hz + 36.1dB = -93.9dBc/Hz @ 100kHz.
Whatever multipliers you use, the process of multiplication it will inevitably increase the Phase Noise.
We believe a PLL/VCO that covers 5-7 GHz will have more phase noise than a x16 multiplied 80 - 120 Mhz PLL output. Even if we have an extra 36.1dB phase noise. We wonder what techniques are applied to get the QuickSyn from Phasematrix working with such a low phase noise and 0.001 Hz steps for 2-10 Ghz.
Phasematrix use an exotic method of fractional N synthesis to fast lock with 0.001Hz steps and then switch mixer inputs to use a chain of divide-by-N *multiply-by-M stages up to 10 stages deep for low phase noise.
There is no divider product in the direct path,
Multipliers use harmonic comb filters. There may be a low phase noise 100MHz reference to drive this chain to mix and regulate the low noise LC tuned VCO. DOn't even think of trying to copy it, unless you can do it better in a different way.
I think HP did a similiar method of a frequency generator in the mid 70's that I used. fractional N with dual lock loops then cascade integer multiply/dividers from an OCXO.
If the PLL/VCO approach is optimized for phase noise this should not be the case. What I mean by optimized for phase noise is plot the phase noise of the VCO and the reference on the same graph. Then multiply the reference up to the VCO frequency (in this case add 36 dB). There will be a point where the two curves cross, this is (roughly) where your loop bandwidth should be for optimum phase noise. Then you get the better phase noise of the reference close-in and the better phase noise of the VCO further out.
What if I have a very small subhertz step size?
For the best results, consider using a comb multiplier, e.g. offered by Herotek. Such multipliers are mostly used in microwave PLOs; a dielectric-resonator oscillator is locked on a selected harmonic of the ~100 MHz reference. The phase noise is that of the low-frequency reference, scaled by 20 log PNref +3 dB.
Cascading doublers is not bad but you will need a big number of them and power buffers between them. Doublers need a nominal input power like +10- +17 dBm for a reasonable efficiency. A comb multiplier is one-diode device, nothing else needed. At the microwave output frequency you need a phase detector and the error-voltage loop filter.
This technique is generally applicable. However, sometimes for various reasons you can not operate at this point. I often end up with a larger loop bandwidth because I'm more concerned with lock time than optimal phase noise. In your case with a very fine step size, this would push you in the opposite direction. However, you could consider a frac-n PLL. This would allow fine steps, while optimizing for phase noise, the drawback being higher spurs. The frac-n chips typically offer an option to dither the divide ratio to spread the spur energy (which raises the phase noise), so you would have the option of trading-off between spur levels and phase noise.