Is this another type of PLL?

Assume that we have a very stable 1 Ghz Frequency source like a VCXO or CRO,

If we
1. divide it using a Fractional N counter (Lets say by 100)
2. Compare the /100 output to the output of a 10 Mhz OCXO using a Phase Frequency Detector
3. Use the output of the PFD to calculate the Frequency error
4. Knowing the Frequency error, divide the 1 Ghz Frequency source by another value to get the desired Frequency between 0- 1000Mhz.
5. Repeat step 4 frequently as the Frequency drifts.

I guess the proposed method should be used somewhere, Is this another type of a PLL.
Can we expect better phase noise than a DDS?

Thanks

I guess it would be called FLL and practically, it should be implemented digitally.

Added:
I found this (I guess not for GHz):

http://www.wolfsonmicro.com/document...en/WAN0209.pdf

Thanks for the reference. The FLL described in the document uses again a VCO just like the PLL.

I guess you look including a programmable divider instead of VCO.

That's right

I dodn't understand the term fractional divider related to a 100:1 divider which would be implemented as integer divder. Dividing 1 GHz to an arbitrary output frequency (using a non-integer ratio) will involve strong jitter. Thus I don't actually understand how the imagined method should work?

Fractional PLL's have fractional N dividers. Do they also introduce strong jitter? I understand that the imagined method cannot tune between 0-1000 Mhz but can produce lower frequencies.

Fractional PLLs always generate some jitter. In a usual fractional design, the non-periodical signal is present at the PFD and mostly removed in the loop filter. Some designs are utilizing a digital PFD with sigma-delta noise shaping to reduce the jitter.

In other words, to get low or at least moderate jitter from a fractional frequency divider, you need a PLL with VCO and loop filter.