Low jitter clock CMOS to LVDS converting, dividing and routing

I want to use ABLJO 160MHz clock generator with two ADC with LVDS clock input and as base digital clock. Please tell the best method to transport clock to ADCs with minimum jitter quality loss. The ADC has option to use CMOS clock but I think LVDS will be better and anyway it's needed to transport clock to digital schematic.

LVDS is probably best. Are the clock source and ADCs on the same board? What distances do the clock signals have to travel?

These are two modules on the one board - ADC and DSP. I will set the ABLJO on ADC module, the distance is about 7cm. Clock for DSP will not travel more than 15cm.
Most of all I am not sure about jitter performance of LVDS drivers and buffers.

A small signal transformer balun will add no jitter to the signal. I've used parts like CX2045 for this purpose. Having to split it into two makes things a bit more complicated. If it were me I would use two baluns right at the clock source to convert to two LVDS pairs, then rout those the majority of the distance to the ADC. Make sure you keep impedance matching and length matching in mind, and all that.

What is your jitter requirement?

I've seen LVDS fanout buffers that had ~100 fs additive jitter. This level of jitter is good enough for *most* ADC applications. Also, since the board will have both analog and digital you have to worry about noise pickup in the clock lines and LVDS is certainly superior there to single ended.

Please advice the most suitable fanout buffer for my application: 160msps 16bit for 40MHz signal. ABLJO has ~100fs jitter with CMOS output; I need 3 LVDS lines loaded with two ADCs (7cm distance) and one FPGA (15cm distance).
I tried searching with google but can not see <500fs buffers.

500 fs huh? here is one with 8 fs:
http://www.hittite.com/products/view...iew/HMC987LP5E

To calculate SNR from rms jitter you can use the following:

SNR = -20*log(2*pi*f*jitter)

If we assume that your 16 bit ADC has an SNR of 90 (15 effective bits), and f=40 MHz, then we can calculate the maximum rms jitter as 125 fs.

Your clock already has 100 fs jitter. The noise from the fanout will be uncorrelated, so the fanout could have up to sqrt(125^2-100^2) = 75 fs. So Biffs part with 8 fs jitter should work great.