passive loop filter design

hi all
I'm going to design some passive loop filter for my PLL.the PLL is fractional.
I have somw documentation about PLL design for integer PLL.and this is my question:Is there any difference between design of passive loop filter for fractional and integer PLLs?
If yes would you please introduce me some sources for that?

For PLL, almost same.
You can use free software to design it, such as ADISimPLL, it's very easy to use and very successful in the domain.
Fractional PLL has more spurs than interger's.