on-chip balun's output imbalance problem
Post your layout first then let's intereprete..
since i could not upload the pic, i'll try to explain it more clearly.
the balun was 1:1, the primary coil was a one turn indcutor with top metal, the the secondary coil was the same pattern as primary coil but was the another metal layer. so the layout is fully differntial, and no metal under-cross each other.
in the simulation, the balun should good property when the center tap was connected to an ideal ground. but if an inductor was insert between center tap and gournd(as layout wire paracitics) , the imbalance came out obviously. Odd~
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since i could not upload the pic, i'll try to explain it more clearly.
the balun was 1:1, the primary coil was a one turn indcutor with top metal, the the secondary coil was the same pattern as primary coil but was the another metal layer. so the layout is fully differntial, and no metal under-cross each other.
in the simulation, the balun should good property when the center tap was connected to an ideal ground. but if an inductor was insert between center tap and gournd(as layout wire paracitics) , the imbalance came out obviously. Odd~
Some thought in this configuration:
Besides the inductive coupling, there is also some capacitance between the primary and secondary.
I don't think your geometry has perfect common mode rejection. If you connect the center tap to an ideal ground, you perfectly short the common mode. However, if you connect it to a real ground (=common mode not perfectly shorted) the residual common mode causes the imbalance that you desribed.
yes, i think the main reason is just as you said. the siganl in primary coil was coupled to secondary one. the phenomena was worse at high freq than low freq, which also show the effort of capacitance coupling. But the coupling is along the whole coil, which is distributed, the quantitative analysis is difficult.
I have tried several balun pattern, and the imbalance seems unavoidable, any better idea ?
