Low jitter clock synthesizer

Is anybody know any efficient solution for 500MHz low jitter clock (<0.5ps) generation with duty cycle value of 0.50+-0.01.

Now i want to do PLL for 2GHz output from 25MHz reference and divide by 4 VCO frequency with using duty cycle correction scheme. But i think i cant get so low RMS jitter value on span 100kHz - 100MHz.
Maybe anyone know better solution for this requirements? Thanks!

these are close at < 1 ps

http://www.digikey.com/product-detai...290-ND/1867574

Its very expensive component for using in IC. Maybe anyone know any good and simple ideas for IC design?

Digikey also shows some TXC corp saws at only S7, but they are not in stock. Look around.