Resonance load or (inter-stage) impedance matching for CMOS amplifiers
时间：04-06
整理：3721RD
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Hi all,
Given a millimeter-wave multi-stage common source/cascode CMOS amplifier. Which method would be the proper design: inter-stage conjugate matching or resonance load (adjacent stage should be place close in the layout)?
For CMOS transistor, it is gate-source voltage controlled device, it is more important to provide high voltage (not power) to the gate. So if the adjacent stage is placed very close: resonance load is the proper way, thus complex inter-stage matching is relaxed, chip size is saved. However, in most of state of the arts literature I have reviewed, inter-state matching is often chosen.
Could anyone provide some idea? Thank you very much.
Given a millimeter-wave multi-stage common source/cascode CMOS amplifier. Which method would be the proper design: inter-stage conjugate matching or resonance load (adjacent stage should be place close in the layout)?
For CMOS transistor, it is gate-source voltage controlled device, it is more important to provide high voltage (not power) to the gate. So if the adjacent stage is placed very close: resonance load is the proper way, thus complex inter-stage matching is relaxed, chip size is saved. However, in most of state of the arts literature I have reviewed, inter-state matching is often chosen.
Could anyone provide some idea? Thank you very much.