Input Matching Network question

Hi all,

I came across this RF class-D power amplifier design and want to know, what type of input matching has been used here? I cant really understand the input matching schematic below(shown in the red region). Is it only for matching purpose or is there any other purpose? Could someone please explain it to me?

Thanks a lot.

Is not a particular type of impedance match. The series gate inductors are used to resonate the internal Cgs of the FETs. Also there are two identical high-impedance bias networks (for Vgg), most probably using quarterwave TL, series chokes, and decoupling caps.
The blocking caps (in series with gates) can be used for narrowband matching together with the afferent series TL, and the shunt TL (which goes to Vgg). But this statement is not mandatory in a wideband matching.

Matching to switchmode amp gates isn't an exact science, in my experience. For my class D amps I use an inductor in series with the gate, and then a shunt capacitor. That circuit could work too though.