the scaling-down of the CMOS technology and low power supply

Hi,
I wonder why the scaling-down of the CMOS technology imposes low VDD as in the picture below.
Please help.

Hi, why we have to lower the power supply in CMOS technology as it is scaled down?
I know one of the reasons it about breakdown voltage. With sizes smaller, breakdown voltages also decrease. But, i think it is not the main reason. Can anyone help?