Simulating S53MV's microstrip VCO using different transistors (phasing line lengths)
Hello! I am trying to simulate this VCO using this approach:
1) i make amplifier with interdigital bass filter, make it's S21 phase equal to 0deg. So parallel feedback does not exist.
2) connect this amplifier input with it's output.
again, link with illustration:
http://lea.hamradio.si/~s53mv/spectana/vco.html
i make the same phasing lines, just make amplifier with interdigital bandpass filter first, make it's s21 phase zero and connect to do final oscillator simulation
But here i found one problem: when i try to optimize gate phasing line for more power, there are some other maximums on S21 graph appear with phase near zero. So, when optimized, parallel feedback loop have multiple paths with 360*n phase shift. For example 1.2GHz, and main maximum at 2.4GHz. Does it means that it is better not to optimize this thing, but let it be unoptimized, so only one S21 maximum relates to n*360 phase shift?
These guy almost has no rules and no simulations but these equipments less or more works. He is talent. Wide band VCO s isn't good idea. Big phase nose and so on.
The filter should suppress other S21 amplitude responses, so only the one at 2.4GHz (your desired one) should be zero phase with S21 amplitude above 0dB to sustain oscillation.
S21 could be less as well, -10dB for instance...
Please explain. They taught us that a 0 phase is needed and gain of >1 is necessary to get an oscillator from a loop combination of an active and passive devices.
I had two s21 maximums when tried to optimize, and both phase is near zero and high gain. I cant understand where it comes from, because i altered only gate stub length. Maybe it matched gate to other frequency. Also i reduced microstrip resonator coupling to quaterwave, original is almost halfwave and gives ugly filter s21. Results look well in simulation when keeping gate stub short, enough to couple with resonator, and drain stub longer, tuning overall phase to 360deg. If anybody unsuccessful building this vco i suggest to make gate stub shorter, and reduce resonator coupling area to quarterwave.
Typically you should provide matching as well. Oscillation frequency quite low. The BJTs feel better and matching quite well as well against FETs who works on highest frequencies.
By the way, in the article, I see nothing, concerning FETs. At the moment I have a similar fun. Vivisection for ever.
What frequency did you tried?
And what about -10dB you said. Do you mean somethink like s21 of 0.7, etc? I think it will not oscillate. Only if you provide another higher/lower voltage than in datasheet, or wave somehow leaked through transistor bottom with low losses and made s21 > 1 to sustain oscillation.
I like FET's for their high gain and separate biasing of gate. And also they are good for learning, because from my experince, there are more PDF's can be found in google, where FETs used in oscillators and amplifiers, active antennas. I used their photos and S parameters to check some theory from book "RF Circuit Design Theory and applications Ludwig, Bogdanov". Using design steps from this book i carefully calculated lengths of all microstrips, matching, but get different results. Then i tried simulation. I almost sure that different results does not mean wrong, they just used other criteria, things can be done in too many ways. Most of BJT articles done in lumped components, but i like microstrips. I wanted to try higher frequencies, but without equipment it is total random mess and loss of time, disappointment. So at the moment i enjoy my calculations in SpeqMath and Qucs simulations.
I mean coupling between micro strip lines.
As for FETs of course they are good but my target phase noise don`t
allow to use them.
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