Matching fet multiplier question.

Hello! Please tell me how to match FET multiplier for better performance?

Take S11 at F0 and match to 50 Ohms
Take S22 at n*F0 and match to 50 Ohms

Or:

Take S11 at F0, and put (1/S11) stub at input
Take S22 at n*F0, and put (1/S22) stub at output. In both cases match only phases (make amplitude of inverse = 1)

yes I would match the input at F0 to get power into the fet. But I would also do something about presenting the right impedance to the gate at 2F0, 3F0..nF0

Similarly I would match S22 at NF0, but the question is: what impedance is optimal for that. it is NOT the S22 you would measure at small signal at nF0. Also, as with the input, you would need to present the proper impedance at F0, 2F0, etc.

"proper impedance" might mean an open or short circuit.

You are not really doing impedance matching, but forcing some voltages to be zero or maximum, and in that way shaping the output waveform to look more like nF0 sine wave in the time domain.

Understand. I try to use this minimum configuration:

Input:
1) Match input to 50 Ohms (or to impedance of signal source if it is not 50 Ohms) at F0
2) Put quarterwave stub at 2*F0,3*F0 to zero leaked harmonics at input, so imput waveform not disturbed

Output:
1) Match output to 50 Ohms at n*F0 (wanted harmonic)
2) Put quarterwave stub at F0, so it not interfere with wanted harmonic.