Is it okey to use a counter as a pll integer N divier ?
时间：04-05
整理：3721RD
点击：
Hello,
I am designing a PLL with low output frequency (~350MHz, reference frequency: 10MHz). I want to have a divider ratio from 1 ~ 63.
Because the frequency is low, and divider ratio is not very high, is it ok to just use a synchronous counter synthesized by verilog to work as a divider, instead of using swallow method. Also I am not familiar with the swallow counter.
Any advice?
Thank you
I am designing a PLL with low output frequency (~350MHz, reference frequency: 10MHz). I want to have a divider ratio from 1 ~ 63.
Because the frequency is low, and divider ratio is not very high, is it ok to just use a synchronous counter synthesized by verilog to work as a divider, instead of using swallow method. Also I am not familiar with the swallow counter.
Any advice?
Thank you
You can use an offset PLL.
../imgqa/eboard/Antenna/rf-2zmkyo3u41n.gif
yes you can make a programmable synchronous (or non synchronous) counter. if you are doing one with software instead of actual gates....you can have varying time delays in the division, which would give rise to time jitter (phase noise) so you must be careful.