Why PLDRO can be designed only by SPLD method?

I am looking for a design to implement Phase locked DRO or PLDRO.

During literature survey, I find the only way to implement this is by using a SRD comb generator
and a phase detector to phase lock the Vt-DRO,it requires a sweep circuit too(sampling phase
locked detector,SPLD),which makes it too complicated.(Vt-DRO stands for voltage tunable DRO)

Why can't we use a PFD chip instead to phase lock Vt-DRO?like its done for VCO.It will
make things simpler,no need to use sweep circuit etc.

What is the technical difficulty ,can some one explain?

the DRO is pretty stable, so there is really no reason to need a sweep lock circuit. With the proper type of phase/frequency detector, it will lock up just fine.

also, yes of course it can be phase locked with ANY pll chip. just realize the tuning range is not very big on the oscillator.

What I understand from the literature survey,is that a desired frequency is injected in DRO,to make it resonate and oscillate at the frequency,called "injection locking".

But,otherwise,VCOs are made to oscillate at the desired frequency by sweeping control voltage,when VCO and reference signal are phase locked.
Here all comparison is done at much lower frequency,no need to generate the actual frequency by SRD as its done in PLDRO.