Does the TSMC 40nm pdk inductor model include a shielding strategy?
时间：04-04
整理：3721RD
点击：
Hi all,
I was going through the TSMC 40nm pcell inductor model and I think I can't see any ground or floating shield.
There is a subcell inside the inductor layout pcell view which is called "dummy_loop_diff_DM_sym_ind". I think that subcell relates with OD/PO (red and blue colour) dummy excluded strategy because that layout view contains small rectangle OD/PO cells and does not relate with some new shileding strategy. Right? See the attached file.
Does anyone who has used that process knows if that process uses ANY kind shieding strategy that I might be missing?
Thanks in advancef
I was going through the TSMC 40nm pcell inductor model and I think I can't see any ground or floating shield.
There is a subcell inside the inductor layout pcell view which is called "dummy_loop_diff_DM_sym_ind". I think that subcell relates with OD/PO (red and blue colour) dummy excluded strategy because that layout view contains small rectangle OD/PO cells and does not relate with some new shileding strategy. Right? See the attached file.
Does anyone who has used that process knows if that process uses ANY kind shieding strategy that I might be missing?
Thanks in advancef